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Use of functions,procedures in vhdl

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vhdl function

What is the use of Functions,Procedures in VHDL.?
I know that it is same as in C language.But can anyone explain me in the view if HARDWARE language or hardware circuits.
(like the harware it generates will be more or less)
thank you.
 

vhdl procedure

I never used functions and procedures in VHDL programming, cause I don't like them very much.
You're right when you say that it's more or less like C language, but you always have to think that you are using a hardware description language (not a programming language), otherwise you will easily do some mistakes.
When you call a procedure or a function (the difference is very little) in a process (you can call it only inside a process!) the portion of code that you defined before is executed in the process (staements, conditions, etc...). Remember that the statements defined are executed at the same time (not like in C language).
Finally, I think that procedures and functions (that you can define also inside packages) could simplify your code, but on the other hand could assimilate VHDL to C language too much, and this could be dangerous.
 

vhdl functions

Thank you for your answer.
1. apart from the compactness of the program,will hardware become less or reduce ??
2. Can we say that using procedures,packages,functions as good programming in vhdl??
3.Is it really worthy to use functions,procedures and pacakges in the programming??

4. "but on the other hand could assimilate VHDL to C language too much, and this could be dangerous".
i did not understand the above statement.



Thank you.
 

function in vhdl

Well, I talk about my opinion
I think all of the Designer wanted the Code simple and understandable. so when we use C language we all want short the code and compress the program.
But we design hardware language not the same as C.the terminal aim is convert VHDL to real circuit,so the simple code is not represent simple circuit.I consider when you design VHDL you need to know the basic idea of Hardware and some thoughts. there is not need the simple code but the simple circuit.that's all
 

procedure vhdl

>1. apart from the compactness of the program,will hardware become less or reduce ??

No hardware reduction...nothing that you can't also do without using functions and procedures.

>2. Can we say that using procedures,packages,functions as good programming in vhdl??

What do you mean? Using functions, packages and procedures makes some designs more readable and easy to understand but you won't obtain any advantage in term of logic elements usage.

>3.Is it really worthy to use functions,procedures and pacakges in the programming??

I think it isn't, but could help you during your design.

>4. "but on the other hand could assimilate VHDL to C language too much, and this could be dangerous".

While you are doing your project you always have to think to the architecture that the compiler will create from your design, because you are only describing a hardware. Using functions and procedures makes your VHDL design similar to a C program IN APPEARENCE, but it's NOT true...so you could do some mistakes!
 

function vhdl

Thank you for ur replies..
 

vhdl procedures

hello GertDalPozzo........

you wrote that "you can call it only inside a process!"...........
that is wrong.you can call function and procedures outside process also.

in function and procedure we can use only sequential statements but we can use them as a concurrent statement also.

using them you can use any sequential statement outside process also.......

amit gangwar
 

functions in vhdl

Are you sure?
I read you can use them only inside processes.
From "VHDL Cookbook" by Ashenden:
"We can write a procedure declaration in the declarative part of an architecture body or a process. If a procedure is included in an architecture body’s declarative part, it can be called from within any of the processes in the architecture body. On the other hand, declaring a procedure within a process hides it away from use by other processes"
 

vhdl function example

yes, i m 100 % sure....
i m using it....
the best place of writing function and procedure is the package.....
1.)if you declare subprogram declaration and body both in process -->> then you can use them only in that process.
2.)if you declare subprogram declaration and body in architecture -->> then you can use them in all the process and within architecture also.
3.)if you declare subprogram declaration and body in package body -->> then you can use them only in that package body and can not use in any other program.
4.)if you declare subprogram declaration in package declaration and body in the package body -->> then you can use them any where.....package body, any architecture, any process.
for that you have to just add that package in your project.and declare it below the library declaration.


use work.my_pack.all;
here work is library where package is stored.
my_pack is the file name......

amit gangwar
 

procedures in vhdl

Functions/procedure in HDL operate v.differently than those in C language.
in a programming language such as C, any function when called, will refer to same code somewhere in the memory. i.e there is a single peice of code, which is referred each time function is called.
Whereas
in VHDL, each time you call a function, a dedicated hardware is synthesized corresponding to it. If you call a function 10 times, the hardware will have 10 instances of that function.
And please do NOT call vhdl a programming language, its a hardware description language used to describe hardware, it cannot program any cpu to do a job for us as C or C++ does.

Use of functions/procedure in VHDL helps a lot to write a compact readable code. Use them as much as possible. The only problem is, that you cannot trace the variables inside the function on waveform window, which is a problem at times.

Here are some examples of vhdl functions

http://www.vlsiip.com/vhdlf.html

Kr,
Avi
http://www.vlsiip.com
 
vhdl procedure declaration

use functions to impliment non syntiazble construction for example STD_LOGIC_VECTOR to integer converter.

Also functions are very useful for test benches

Use separate entities, if you want to create component and pouplate it 10 times
 

you cannot use any kind of edge detection inside a function or package.Remember that functions are used to represent combinatorial circuits.
A clock is used in a sequential circuit.So clock cannot be used.
 

okkay,
now if i have a sequential program with a clk in sensitivity list,say named "modulus",and i want to use it in another sequential main program( main program also sense clk) ,where this "modulus" operation is used many times,how can i use it???
 

A sequential program with a clk in sensitivity list, e.g. a serial multiplier, divider or modulus calculation unit can be only instantiated as a component in concurrent code, outside another process. But a component instance can be connected to a process by signals. You have to consider the "execution" time of the sequential program and use e.g. handshake signals to synchronize the data processing.
 
I want to implement this method attached with this post in vhdl code,
my modulus program is really big & clk sensitive,
you advise to use port mapping in outside of the process of main program considering the ports of modulus programs as signal,but u see there is for loop,where im trying to use modulus operation,how is it possible??
 

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Are you aware of the meaning of a for ..loop iteration scheme in VHDL? It means generating parallel logic, k-1 instances of it. K must be known at compile time for the logic to be synthesizable. (And it must be sufficient low to fit the limited logic resources, of course).

If it's intended this way, a for ... generate construct would be the adequate means to make k-1 component instances.

But it doesn't work with your design, because the modulus calculation is already serialized and the next "for" step can't be started before the previous has finished. So it turns out as a another level of serial execution. It can't be represented by a for loop, as you could already know from the previous serial divider discussion. Use a state machine instead.
 

if I use a state machine in my main program then there must be a main :process(CLK),
and if i consider a state,'modulus" where my mod operation has been done,this modulus also has a mod :process(CLK),is it possible that a mod :proces(clk) exist inside another main : process??,
i think not possible
 

You're thinking too much like software. This is not software, it's hardware.

Go and learn about digital electronics. When you understand that, you can think of the circuit needed to solve this problem, and then you can use VHDL to DESCRIBE your circuit. it's hardware description (not programming) language.
 

if I use a state machine in my main program then there must be a main :process(CLK)
Click to expand...
Right. But the serial modulus instance can reside outside the process and be synchronized by state signals.

You can also use a parallel divider/modulus unit, that calculates the result within one clock cycles, or a few of them. But the iteration loop would be most likely serialized by a state machine anyway.
 

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