rahdirs
Advanced Member level 1
Hi,
I was recently asked this question in a Logic Design/DV interview,
Suppose you have the following, what should be the bit width of c,d,e ? The interviewer said that the answers of my d & e were wrong. For e my answer was based on 3 as 2'b11 which would give a width of 18. What do you guys think ?
I was recently asked this question in a Logic Design/DV interview,
Suppose you have the following, what should be the bit width of c,d,e ? The interviewer said that the answers of my d & e were wrong. For e my answer was based on 3 as 2'b11 which would give a width of 18. What do you guys think ?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 // The code is my interpretation of his question. logic [9:0] a; // can be anything, 9 & 8 were chosen as random logic [8:0] b; logic [?:0] c; // 17 wide ? logic [?:0] d; // 18 wide ? logic [?:0] e; // ?? always @(posedge clk) begin // Assume you can finish in 1 cycle c <= a*b; // I think c should be at least 8+9 bits wide ? d <= a*b + 1'b1; // d should be atleast 17 (^) + 1 bits wide ? e <= a*b + 3; // what does the 3 here mean ? //In my 2-3 years of RTL experience I only saw people using the syntax 2'b11 or something like that. //The interviewer was interested in what would verilog interpret the 3 as ? Is it hex by default ? 4'h3 ?? end