electriccc01
Newbie level 1
How to make 3 forward 2 back counter cİrcuİt ? Please help me ...
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You didn't actually test your design idea. It doesn't work.another possibility could be to consider the counter as a state machine with two states: up and down. It could be something like that
Hi,
8 posts now without reaction of the OP.
It seems the OP is not interested in communication.
And we may discuss endlessly about the lack of information...
Klaus
I like schematics. For sure the "software drawn" are more nice, but often they don't contain more informations than hand drawn.... Whoops, that thing that looks like a children's drawing (sadly, I did it!) was meant for electricc01, not Klaus who is an experienced engineer, obviously..
Hi,
It is quite simple to implement this. You need to have a counter, a direction signal and a comparator. Of course you would need clock and reset signals. Now, when the direction is forward, you increment the counter. When the counter value is 2 (i.e. the third count, having gone through states 0, 1, and now, 2) and the direction is forward, then you make the direction back and you reset the counter.
When the direction is backward and the counter value is 1 (i.e. the second count, having gone through 0, and now, 1), then you make the direction forward and you reset the counter.
I haven't mentioned that the logic is sensitive to the clock signal and I how you picture that it is.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 process(clk) begin if clk = '1' and clk'event then cnt_int <= cnt + 1; if up = '1' then if cnt_int = 2 then cnt_int <= (others => '0'); up <= '0'; end if; else -- down if cnt_int = 1 then cnt_int <= (others => '0'); end if; end if; if up = '1' then cnt <= cnt + 1; else cnt <= cnt - 1; end if; end if; end process;
For that sequence, the code could be:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 process(clk) begin if clk = '1' and clk'event then cnt_int <= cnt + 1; if up = '1' then if cnt_int = 2 then cnt_int <= (others => '0'); up <= '0'; end if; else -- down if cnt_int = 1 then cnt_int <= (others => '0'); end if; end if; if up = '1' then cnt <= cnt + 1; else cnt <= cnt - 1; end if; end if; end process;
@electricc01, could you provide more details on the sequence you would like to generate?
... I was considering cnt_int = 1 to be the start of the count...
A necessary correction, see post #15.I can see where the direction (up) is toggled from '1' to '0' on line 8, but there is no where that it is toggled from '0' to '1'.
Also, I see conflict with the increment of cnt_int with clock on line 4 and its conditional reset on line 7 and line 12.