matriX_1500
Junior Member level 1
Hi, I'm using a VHDL code downloaded from GitHub to Drive a UART communication.
Here
I want to Use 250000 Baud Rate. So according to the top of VHDL file explanation, while my I_clk is 50MHz, I set:
I_clk_baud_count <= X"00C8";--means 200
it seems that the tx_clk should be 40us, but it is 40040ns in simulation.
Is it wrong according to the code?
Here
I want to Use 250000 Baud Rate. So according to the top of VHDL file explanation, while my I_clk is 50MHz, I set:
I_clk_baud_count <= X"00C8";--means 200
it seems that the tx_clk should be 40us, but it is 40040ns in simulation.
Is it wrong according to the code?