Sofus
Newbie level 1
Hello,
I am working on an FPGA design where a 20 bit signal is transferred from one component to another component, where a procedure is performed using the 20-bit signal. The calculation performed in the procedure is multiplying the 20 bit signal by 0.00034, or 680/2000000, and then placing this value into a signal of the integer type. However this generates a negative slack for the transfer of data between the register of the 20 bit signal in the first component, and the register of the integer signal in the second component. When I look at the data path in the timing report, it seems that the bulk of the delay is due to the calculation performed in the second component. Is there a less time consuming way to perform the calculation? The calculation in the procedure looks like this at the moment:
I am working on an FPGA design where a 20 bit signal is transferred from one component to another component, where a procedure is performed using the 20-bit signal. The calculation performed in the procedure is multiplying the 20 bit signal by 0.00034, or 680/2000000, and then placing this value into a signal of the integer type. However this generates a negative slack for the transfer of data between the register of the 20 bit signal in the first component, and the register of the integer signal in the second component. When I look at the data path in the timing report, it seems that the bulk of the delay is due to the calculation performed in the second component. Is there a less time consuming way to perform the calculation? The calculation in the procedure looks like this at the moment:
Code:
-- Calculates distance in centimeters
PROCEDURE calculate_distance
(
SIGNAL p_counter_data_in : IN std_logic_vector(19 downto 0);
SIGNAL p_distance_data_out : OUT integer
) IS
BEGIN
p_distance_data_out <= to_integer(unsigned(p_counter_data_in) * 680/2000000);
END calculate_distance;