promach
Advanced Member level 4
For https://paste.ubuntu.com/p/cR6rtvxs7x/ and https://i.imgur.com/ROlyd53.png , why doesn't rCount increment its value at t=50ns when rState=2'd1 and CHNL_RX_DATA_VALID=1?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 // ---------------------------------------------------------------------- // Copyright (c) 2016, The Regents of the University of California All // rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: // // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following // disclaimer in the documentation and/or other materials provided // with the distribution. // // * Neither the name of The Regents of the University of California // nor the names of its contributors may be used to endorse or // promote products derived from this software without specific // prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH // DAMAGE. // ---------------------------------------------------------------------- //---------------------------------------------------------------------------- // Filename: chnl_tester.v // Version: 1.00.a // Verilog Standard: Verilog-2001 // Description: Sample RIFFA channel user module. Designed to exercise // the RIFFA TX and RX interfaces. Receives data on the // RX interface and saves the last value received. Sends // the same amount of data back on the TX interface. The // returned data starts with the last value received, // resets and increments to end with a value equal to the // number of (4 byte) words sent back on the TX interface. // Author: Matt Jacobsen // History: @mattj: Version 2.0 //----------------------------------------------------------------------------- `timescale 1ns/1ns module chnl_tester #( parameter C_PCI_DATA_WIDTH = 9'd32 ) ( input CLK, input RST, output CHNL_RX_CLK, input CHNL_RX, output CHNL_RX_ACK, input CHNL_RX_LAST, input [31:0] CHNL_RX_LEN, input [30:0] CHNL_RX_OFF, input [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA, input CHNL_RX_DATA_VALID, output CHNL_RX_DATA_REN, output CHNL_TX_CLK, output CHNL_TX, input CHNL_TX_ACK, output CHNL_TX_LAST, output [31:0] CHNL_TX_LEN, output [30:0] CHNL_TX_OFF, output [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA, output CHNL_TX_DATA_VALID, input CHNL_TX_DATA_REN ); reg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'b0}}; reg [31:0] rLen=0; reg [31:0] rCount=0; reg [1:0] rState=0; assign CHNL_RX_CLK = CLK; assign CHNL_RX_ACK = (rState == 2'd1); assign CHNL_RX_DATA_REN = (rState == 2'd1); assign CHNL_TX_CLK = CLK; assign CHNL_TX = (rState == 2'd3); assign CHNL_TX_LAST = 1'd1; assign CHNL_TX_LEN = rLen; // in words assign CHNL_TX_OFF = 0; assign CHNL_TX_DATA = rData; assign CHNL_TX_DATA_VALID = (rState == 2'd3); always @(posedge CLK or posedge RST) begin if (RST) begin rLen <= 0; rCount <= 0; rState <= 0; rData <= 0; end else begin case (rState) 2'd0: begin // Wait for start of RX, save length if (CHNL_RX) begin rLen <= CHNL_RX_LEN; rCount <= 0; rState <= 2'd1; end end 2'd1: begin // Wait for last data in RX, save value if (CHNL_RX_DATA_VALID) begin rData <= CHNL_RX_DATA; rCount <= rCount + (C_PCI_DATA_WIDTH/32); end if (rCount >= rLen) rState <= 2'd2; end 2'd2: begin // Prepare for TX rCount <= (C_PCI_DATA_WIDTH/32); rState <= 2'd3; end 2'd3: begin // Start TX with save length and data value if (CHNL_TX_DATA_REN & CHNL_TX_DATA_VALID) begin rData <= {rCount + 2'd4, rCount + 2'd3, rCount + 2'd2, rCount + 2'd1}; rCount <= rCount + (C_PCI_DATA_WIDTH/32); if (rCount >= rLen) rState <= 2'd0; end end endcase end end /* wire [35:0] wControl0; chipscope_icon_1 cs_icon( .CONTROL0(wControl0) ); chipscope_ila_t8_512 a0( .CLK(CLK), .CONTROL(wControl0), .TRIG0({3'd0, (rCount >= 800), CHNL_RX, CHNL_RX_DATA_VALID, rState}), .DATA({442'd0, CHNL_TX_DATA_REN, // 1 CHNL_TX_ACK, // 1 CHNL_RX_DATA, // 64 CHNL_RX_DATA_VALID, // 1 CHNL_RX, // 1 rState}) // 2 ); */ endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 // Testbench module test; parameter C_PCI_DATA_WIDTH = 9'd128; // NUMBER_OF_BITS_PER_TRANSACTION reg CLK; reg RST; wire CHNL_RX_CLK; reg CHNL_RX; wire CHNL_RX_ACK; reg CHNL_RX_LAST; reg [31:0] CHNL_RX_LEN; reg [30:0] CHNL_RX_OFF; reg [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA; reg CHNL_RX_DATA_VALID; wire CHNL_RX_DATA_REN; wire CHNL_TX_CLK; wire CHNL_TX; reg CHNL_TX_ACK; wire CHNL_TX_LAST; wire [31:0] CHNL_TX_LEN; wire [30:0] CHNL_TX_OFF; wire [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA; wire CHNL_TX_DATA_VALID; reg CHNL_TX_DATA_REN; // Instantiate design under test chnl_tester #( .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH) ) riffa_channel ( /*Signals to receive from PC via RIFFA core, transmit to FPGA via this chnl_tester module*/ .CLK(CLK), .RST(RST), .CHNL_RX_CLK(CHNL_RX_CLK), .CHNL_RX(CHNL_RX), .CHNL_RX_ACK(CHNL_RX_ACK), .CHNL_RX_LAST(CHNL_RX_LAST), .CHNL_RX_LEN(CHNL_RX_LEN), .CHNL_RX_OFF(CHNL_RX_OFF), .CHNL_RX_DATA(CHNL_RX_DATA), .CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID), .CHNL_RX_DATA_REN(CHNL_RX_DATA_REN), /*Signals to transmit to PC via RIFFA core, receive from FPGA via this chnl_tester module*/ .CHNL_TX_CLK(CHNL_TX_CLK), .CHNL_TX(CHNL_TX), .CHNL_TX_ACK(CHNL_TX_ACK), .CHNL_TX_LAST(CHNL_TX_LAST), .CHNL_TX_LEN(CHNL_TX_LEN), .CHNL_TX_OFF(CHNL_TX_OFF), .CHNL_TX_DATA(CHNL_TX_DATA), .CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID), .CHNL_TX_DATA_REN(CHNL_TX_DATA_REN) ); initial begin // Dump waves $dumpfile("dump.vcd"); $dumpvars(0); CLK = 0; RST = 0; CHNL_RX = 0; CHNL_RX_LAST = 1; CHNL_RX_LEN = 0; CHNL_RX_OFF = 0; CHNL_RX_DATA = 10; CHNL_RX_DATA_VALID = 0; CHNL_TX_ACK = 0; CHNL_TX_DATA_REN = 0; #20 RST = 1; #20 RST = 0; #10 CHNL_RX = 1; CHNL_RX_LEN = 4; CHNL_RX_DATA_VALID = 1; #20 CHNL_RX_DATA_VALID = 0; #80 CHNL_TX_ACK = 1; #20 CHNL_TX_ACK = 0; CHNL_TX_DATA_REN = 1; CHNL_RX = 0; #40 CHNL_TX_DATA_REN = 0; #400 $finish; end always@(posedge CLK) begin if(CHNL_RX_DATA_VALID && CHNL_RX_DATA_REN) CHNL_RX_DATA <= CHNL_RX_DATA + 1; end always #10 CLK <= !CLK; endmodule