... when the supply is ON, then it should give me -6V.
For stacked voltage division transistors in separate wells it's of course possible to limit their voltage difference to 1.8V . But in any case - because of a common substrate of a bulk CMOS process - you unavoidably have somewhere the total of 1.8V + |-6V| = 7.8V between two different nodes. A 1.8V process won't tolerate this.