shaiko
Advanced Member level 5
Hello,
I have a DDR3 controller with a 128 bit wide data interface.
Currently there're 5 users connected to using the following architecture:
Each "user" has a 16 to 128 width converting FIFO. The application write data to the 16 bit side.
Each of the 5 128 bit FIFO outputs is connected via a MUX to a custom arbiter I wrote.
With every clock that the DDR3 controller is ready (wait signal inactive), the arbiter issues a select signal to the MUX, strobes a read signal to the appropriate FIFO and writes the data to a predetermined address range (that matches the FIFO number).
The design works well at ~120 MHz but I doubt that it'll scale up well.
I expect the 128 bit wide MUX to become a performance bottleneck as the number of users increases...
How did you solve similar problems?
I have a DDR3 controller with a 128 bit wide data interface.
Currently there're 5 users connected to using the following architecture:
Each "user" has a 16 to 128 width converting FIFO. The application write data to the 16 bit side.
Each of the 5 128 bit FIFO outputs is connected via a MUX to a custom arbiter I wrote.
With every clock that the DDR3 controller is ready (wait signal inactive), the arbiter issues a select signal to the MUX, strobes a read signal to the appropriate FIFO and writes the data to a predetermined address range (that matches the FIFO number).
The design works well at ~120 MHz but I doubt that it'll scale up well.
I expect the 128 bit wide MUX to become a performance bottleneck as the number of users increases...
How did you solve similar problems?