moonshine8995
Newbie level 6
i want a vhdl code to use lcd of an fpga virtex 6 .
could anyone help me and give me this code?
thanks
could anyone help me and give me this code?
thanks
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No, nobody can help, but you could help yourself by...i want a vhdl code to use lcd of an fpga virtex 6 .
could anyone help me and give me this code?
thanks
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; USE ieee.numeric_std.ALL; entity lcd is port( clk, RxD : in std_logic; LCD_RS, LCD_RW, LCD_E : inout std_logic; LCD_DataBus : out std_logic_vector(7 downto 0); RxD_data_ready :in std_logic; RxD_data : inout std_logic_vector(7 downto 0) ); end lcd; architecture behav of lcd is signal count : integer; signal Received_Escape : std_logic; signal Received_Data : std_logic; signal LCD_instruction : std_logic; begin LCD_RW <= '0'; LCD_DataBus <= RxD_data; Received_Escape <= (RxD_data_ready) and (RxD_data:='0'); Received_Data <=(RxD_data_ready) and (RxD_data>0); process(clk) begin if rising_edge(clk) then if(Received_Data='1') then count <= count + 1; if(count>0) then count <= count + 1; -- activate LCD_E for 6 clocks, so at 25MHz, that's 6x40ns=240ns end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then if(LCD_E ='0')then LCD_E <= Received_Data; if (count/=6)then LCD_E <= std_logic_vector(to_unsigned(count, 1)); --reg LCD_instruction; end if; end if; end if; end process; process (clk) begin if rising_edge(clk) then if(LCD_instruction='0')then LCD_instruction <= Received_Escape; if (count/=7)then LCD_instruction <= std_logic_vector(to_unsigned(count, 1)); end if; end if; end if; end process; LCD_RS <= not(LCD_instruction); end behav;
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 module LCDmodule(clk, RxD, LCD_RS, LCD_RW, LCD_E, LCD_DataBus); input clk, RxD; output LCD_RS, LCD_RW, LCD_E; output [7:0] LCD_DataBus; wire RxD_data_ready; wire [7:0] RxD_data; async_receiver deserialer(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data)); assign LCD_RW = 0; assign LCD_DataBus = RxD_data; wire Received_Escape = RxD_data_ready & (RxD_data==0); wire Received_Data = RxD_data_ready & (RxD_data!=0); reg [2:0] count; always @(posedge clk) if(Received_Data | (count!=0)) count <= count + 1; // activate LCD_E for 6 clocks, so at 25MHz, that's 6x40ns=240ns reg LCD_E; always @(posedge clk) if(LCD_E==0) LCD_E <= Received_Data; else LCD_E <= (count!=6); reg LCD_instruction; always @(posedge clk) if(LCD_instruction==0) LCD_instruction <= Received_Escape; else LCD_instruction <= (count!=7); assign LCD_RS = ~LCD_instruction; endmodule
and lineLCD_E <= std_logic_vector(to_unsigned(count, 1));
LCD_instruction <= std_logic_vector(to_unsigned(count, 1));
and these are the errorsType conversion (to ieee.std_logic_1164.STD_LOGIC_VECTOR) conflicts with expected type ieee.std_logic_1164.STD_LOGIC
for linenear ":=": (vcom-1576) expecting ')'.
andReceived_Escape <= (RxD_data_ready) and (RxD_data:='0');
and(vcom-1581) No feasible entries for infix operator 'and'.
for lineType error resolving infix expression "and" as type ieee.std_logic_1164.STD_LOGIC.
thanks for helping me.Received_Data <=(RxD_data_ready) and (RxD_data>0);