grezzoman
Newbie level 1
Hello friends!
Since I need to add an ADC in a FPGA project (MAX 10, quartus 17) I tried to donwload some example from altera cloud, like the one below:
https://cloud.altera.com/devstore/p...for-use-with-board-test-system-monitor-panel/
After compilation quartus reports that no logic depends on input clock (to ADC) and that all pin connected to tha ADC dataout are stacked@gnd.
No ADC example from altera cloud help me, always the same problem...
Can somebody help me in this trip? I'm new in FPGA programming and I can't understand why I'm wrong..
Thanks in advance,
Regards!
Since I need to add an ADC in a FPGA project (MAX 10, quartus 17) I tried to donwload some example from altera cloud, like the one below:
https://cloud.altera.com/devstore/p...for-use-with-board-test-system-monitor-panel/
After compilation quartus reports that no logic depends on input clock (to ADC) and that all pin connected to tha ADC dataout are stacked@gnd.
No ADC example from altera cloud help me, always the same problem...
Can somebody help me in this trip? I'm new in FPGA programming and I can't understand why I'm wrong..
Thanks in advance,
Regards!