gautamraavi
Newbie level 5
Hi
I am new to cadence virtuoso, trying to do some timing analysis on the SRAM.
I have built the SRAM cell layout using the cadence virtuoso .
I would like to know how can i convert the layout into VHDL or Verilog codes or the netlist?
And also would like to know which best tool to do timing analysis?
I am new to cadence virtuoso, trying to do some timing analysis on the SRAM.
I have built the SRAM cell layout using the cadence virtuoso .
I would like to know how can i convert the layout into VHDL or Verilog codes or the netlist?
And also would like to know which best tool to do timing analysis?