Help me start building a VGA interface

Hi Every one,
actually this is my first time to make a new topic here but really i need help.
My graduation project in the faculty required a VGA interface .
as i use a FPGA Board "Spartan-3E" , soft core processor "MicroBlaze", and embedded operating system "uClinux".
the project objective is to display text, and really i donot know from where i can start to Build the VGA interface .
so if any one knows the steps of building such that stuff or give me any help , that would be very nice
thanks in advance.

vga interface

U can use Video DAC from cypress or analog devices for VGA output.

opb vga code

http://home.freeuk.com/fpgaarcade/displaytest.htm
**broken link removed**
**broken link removed**

vga interfacing in vhdl

If you're using an "officially supported board" (Spartan 3E500 Starter Kit, or Spartan 3E1600 Microblaze Kit), then the Xilinx Platform Studio/EDK CD comes with fully pre-built peripherals -- synthesizeable RTL and C-software device driver (for the embedded operating-system.)

If you're using the EDK, then check there first.

edk vga vhdl

boardlanguage said:

If you're using an "officially supported board" (Spartan 3E500 Starter Kit, or Spartan 3E1600 Microblaze Kit), then the Xilinx Platform Studio/EDK CD comes with fully pre-built peripherals -- synthesizeable RTL and C-software device driver (for the embedded operating-system.)

If you're using the EDK, then check there first.

Click to expand...

Where you found in these any VGA related stuff ???

vga interface + fpga

thx so much for help
and i think im so close to my target through this link

**broken link removed**

but unfortunatly some links in it doesnot work (specially for VGA) so if any one can give me another link to the same link it will be so fine
thx in advance
byebye

Added after 13 minutes:

Hi,
actually after searching i found my project need, OPB-VGA Core
and i found its link doesnot working as i have mentioned in my last replay
thx in advance
byebye

interface vga vhdl

Yes, these links is down ...

Some VGA related stuff:
**broken link removed**
**broken link removed**

sysclk microblaze spartan3e

Thx again for helping
but what i have tested with the latest links that it is not going well with the work i have done before
it is cannot be integrated
so if any body can give me a link for a separate vhdl core of the OPB_VGA
may be i can integrate it with my other work
and thanks in advance
byebye

vga controller opb interface

hoooooooooooooooooooooooooooooooooooooooooooooooooooooo
yahooooooooooooo Done Done
Thanks for every one has Helped me

And Now can any one tell me How to integrate the VGA Application on the uClinux

Thx in Advance

fpga dff vga

i have some code for vga interface. and you can use it, i think.
I tested this somple and it works!
For any time scales you can define other numeric values acording VESA standarts (GTF timings)

TITLE "VGA_sync";
-- Version 1.0
-- Copyright Rune Baeverrud, October 6, 1997


INCLUDE "lpm_counter.inc";
INCLUDE "lpm_compare.inc";

SUBDESIGN VGA_sync
(
SysClk: INPUT;
Enable: INPUT=VCC;

h_sync, v_sync : OUTPUT;
video, pix_en, frame : OUTPUT;
h_cnt[9..0], v_cnt[9..0] : OUTPUT;
pixel_address[19..0]: OUTPUT;
)

VARIABLE
h_state : MACHINE WITH STATES (h_video, h_delay1, h_sync_now, h_delay2);
v_state : MACHINE WITH STATES (v_video, v_delay1, v_sync_now, v_delay2);
h_counter : LPM_COUNTER WITH (LPM_WIDTH=10);
v_counter : LPM_COUNTER WITH (LPM_WIDTH=10);
v_enable : NODE;
h_cnt_1d[9..0]: DFF;
v_cnt_1d[9..0]: DFF;
frame_ff : DFF;

BEGIN
h_counter.clock = SysClk;
v_counter.clock = SysClk;
h_state.clk = SysClk;
v_state.clk = SysClk;
h_cnt_1d[].clk = SysClk;
v_cnt_1d[].clk = SysClk;
frame_ff.clk = SysClk;

h_counter.clk_en = Enable;
h_state.ena = Enable;

v_enable = Enable AND LPM_COMPARE(h_counter.q[], 699,,,)
WITH (LPM_WIDTH=10, ONE_INPUT_IS_CONSTANT="YES")
RETURNS (.aeb);
v_counter.clk_en = v_enable;
v_state.ena = v_enable;

h_cnt_1d[] = h_counter.q[];
h_cnt[] = h_cnt_1d[];

v_cnt_1d[] = v_counter.q[];
v_cnt[] = v_cnt_1d[];

pixel_address[] = (v_cnt_1d[], h_cnt_1d[]);

video = DFF(h_video AND v_video, SysClk,,);

h_sync = DFF(NOT h_sync_now, SysClk,,);
v_sync = DFF(NOT v_sync_now, SysClk,,);

pix_en = DFF(Enable AND h_video AND v_video, SysClk,,);
frame = DFF(frame_ff, SysClk,,);

CASE h_state IS
WHEN h_video =>
IF LPM_COMPARE(h_counter.q[], 639,,,)
WITH (LPM_WIDTH=10, ONE_INPUT_IS_CONSTANT="YES")
RETURNS (.aeb) THEN
h_state = h_delay1;
ELSE h_state = h_video;
END IF;
WHEN h_delay1 =>
IF LPM_COMPARE(h_counter.q[], 658,,,)
WITH (LPM_WIDTH=10, ONE_INPUT_IS_CONSTANT="YES")
RETURNS (.aeb) THEN
h_state = h_sync_now;
ELSE h_state = h_delay1;
END IF;
WHEN h_sync_now =>
IF LPM_COMPARE(h_counter.q[], 755,,,)
WITH (LPM_WIDTH=10, ONE_INPUT_IS_CONSTANT="YES")
RETURNS (.aeb) THEN
h_state = h_delay2;
ELSE h_state = h_sync_now;
END IF;
WHEN h_delay2 =>
IF LPM_COMPARE(h_counter.q[], 799,,,)
WITH (LPM_WIDTH=10, ONE_INPUT_IS_CONSTANT="YES")
RETURNS (.aeb) THEN
h_state = h_video;
h_counter.sclr = VCC;
ELSE h_state = h_delay2;
END IF;
END CASE;

CASE v_state IS
WHEN v_video =>
IF LPM_COMPARE(v_counter.q[], GND, 479,,,)
WITH (LPM_WIDTH=10, ONE_INPUT_IS_CONSTANT="YES")
RETURNS (.aeb) THEN
v_state = v_delay1;
ELSE v_state = v_video;
END IF;
WHEN v_delay1 =>
IF LPM_COMPARE(v_counter.q[], GND, 492,,,)
WITH (LPM_WIDTH=10, ONE_INPUT_IS_CONSTANT="YES")
RETURNS (.aeb) THEN
v_state = v_sync_now;
ELSE v_state = v_delay1;
END IF;
WHEN v_sync_now =>
IF LPM_COMPARE(v_counter.q[], GND, 494,,,)
WITH (LPM_WIDTH=10, ONE_INPUT_IS_CONSTANT="YES")
RETURNS (.aeb) THEN
v_state = v_delay2;
ELSE v_state = v_sync_now;
END IF;
WHEN v_delay2 =>
IF LPM_COMPARE(v_counter.q[], 524,,,)
WITH (LPM_WIDTH=10, ONE_INPUT_IS_CONSTANT="YES")
RETURNS (.aeb) THEN
v_state = v_video;
v_counter.sclr = VCC;
frame_ff = v_enable;
ELSE v_state = v_delay2;
END IF;
END CASE;

END;

Added after 4 minutes:

use this table values (system clock freq are 25,50,75 MHz for 3 video modes):

----------------------------------------------------------
% Стандартные видеорежимы %
----------------------------------------------------------
% [*User-Defined_mode,(640X480X60Hz)] %
constant VIDEO_MODE_640_480_60Hz_H_DISP = 640;
constant VIDEO_MODE_640_480_60Hz_H_FPORCH = 16;
constant VIDEO_MODE_640_480_60Hz_H_SYNC = 96;
constant VIDEO_MODE_640_480_60Hz_H_BPORCH = 48;
constant VIDEO_MODE_640_480_60Hz_H_SYNC_POL = 0;
constant VIDEO_MODE_640_480_60Hz_V_DISP = 480;
constant VIDEO_MODE_640_480_60Hz_V_FPORCH = 11;
constant VIDEO_MODE_640_480_60Hz_V_SYNC = 2;
constant VIDEO_MODE_640_480_60Hz_V_BPORCH = 31;
constant VIDEO_MODE_640_480_60Hz_V_SYNC_POL = 0;

% [*User-Defined_mode,(800X600X72Hz)] %
constant VIDEO_MODE_800_600_72Hz_H_DISP = 800;
constant VIDEO_MODE_800_600_72Hz_H_FPORCH = 56;
constant VIDEO_MODE_800_600_72Hz_H_SYNC = 120;
constant VIDEO_MODE_800_600_72Hz_H_BPORCH = 64;
constant VIDEO_MODE_800_600_72Hz_H_SYNC_POL = 1;
constant VIDEO_MODE_800_600_72Hz_V_DISP = 600;
constant VIDEO_MODE_800_600_72Hz_V_FPORCH = 37;
constant VIDEO_MODE_800_600_72Hz_V_SYNC = 6;
constant VIDEO_MODE_800_600_72Hz_V_BPORCH = 23;
constant VIDEO_MODE_800_600_72Hz_V_SYNC_POL = 1;

% [*User-Defined_mode,(1024X768X70Hz)] %
constant VIDEO_MODE_1024_768_70Hz_H_DISP = 1024;
constant VIDEO_MODE_1024_768_70Hz_H_FPORCH = 24;
constant VIDEO_MODE_1024_768_70Hz_H_SYNC = 136;
constant VIDEO_MODE_1024_768_70Hz_H_BPORCH = 144;
constant VIDEO_MODE_1024_768_70Hz_H_SYNC_POL = 0;
constant VIDEO_MODE_1024_768_70Hz_V_DISP = 768;
constant VIDEO_MODE_1024_768_70Hz_V_FPORCH = 3;
constant VIDEO_MODE_1024_768_70Hz_V_SYNC = 6;
constant VIDEO_MODE_1024_768_70Hz_V_BPORCH = 29;
constant VIDEO_MODE_1024_768_70Hz_V_SYNC_POL = 0;

vga interface fpga

http://zheharry.googlepages.com/opb_vga_v1_00_a.tgz

Actually I never try it, and have no idea where it comes from (grab it for long time ago).
But I still hope it helps. ;-)

http://zheharry.googlepages.com/opb_ps2_v1_01_a.tgz
I uploaded the ps2 interface if anyone is interested.
(never tried, again )

vga interfacing with fpga

Is anyone who have resources for vga controller for virtex II pro on vhdl ??????????

opb_vga+xilinx

Please mister Shaiboub can you tell us exactly with the steps and the files you used in your procedure.
By the way I used the files opb_vga and opb_ps2 that mister zheharry had uploaded but there is some kind of missing vhdl package called console_common_v1_00_a that the EDK 9.1i requires, if anyone has this package please upload it.
Many thanks....................

vga protocol fpga

cypress from altera have the vga interface code in varilog,for generating the test pattern on vga monitor.

thanx

vga fpga interface

what do you mean cypress from Altera???

fpga vga interface

Please People any one send the console_common_v1_00_a library.
Please Please Please Please Qickly QicklyQicklyQicklyQicklyQickly

opb vga

Hi extra_brain,

I'm the writer of the ps2 and vga cores. It was my thesis topic. If you are still interested, send an email to me: szalai.andras@t-online.hu.

Bye

vga interface connection

ok