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Parasitic Delay Calculation in CMOS circuit

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kiran81077

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Hi,

Can anyone explain how parasitic delay calculated in a domino CMOS circuit.
I know the values for a DOMINO Inverter it is 5/6, and for a Static CMOS it is 1. Also for a 3 input NAND gate it is 4/3 (Domino Circuit) and 3 (Static CMOS).

I would want to know why there is a difference in the Parasitic delay and how it is calculated.

Thanks in advance.
Cheers,

Kiran
 

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