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Getting setup and hold time violation

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srilekha

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Hi all,
I have acheived a frequency of 50 MHz after place and route.

But still i am getting setup and hold time violation when i am running the timing simulation for 50 MHz.

Anyone has idea why its failing for the frequency that it has acheived after place and route?

Thanks & Regards,
Srilekha
 

Have you built the sdf file? Then you have to load it into your simulation software and you should not have any setup and/or hold violation.
If some violation, anyhow, occurs you can try giving a bigger target slack to your place and route software, just to have an additional margin.

PS: the slack after place and route must be positive of course!
 

Hi,
You can try a couple of things:

As suggested above, make sure that you are loading and back annotating the sdf.
Another option is to try running your gate sims at a lower frequency, say 25Mhz. If it passes, then obviously you haven't met timing at 50Mhz.
Also look at your library models and see they are all proper.

Naveen,
http://vlsiforum.com
 

Running the simulation with lower frequency will not get rid of the HOLD violations.

Make sure your STA is clean and that you are using the SDF to proper annotate the simulation. you should see some message like: “SDF Backannotation Successfully Completed.”

cheers
 

perhaps there is asynchronous signal.

or maybe other reasons.



srilekha said:
Hi all,
I have acheived a frequency of 50 MHz after place and route.

But still i am getting setup and hold time violation when i am running the timing simulation for 50 MHz.

Anyone has idea why its failing for the frequency that it has acheived after place and route?

Thanks & Regards,
Srilekha
Click to expand...
 

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