Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I think that pin location decision depends totally on the design and the floorplan made for the whole chip.
The place and route guys need to get a LEF file . This LEF file contains all the information about the cell borders , pin locations and the regions were the routing is permitted.
You can put the pins anywhere in the cell if the design is not harmed by this choice. But in case of not placing the ports at the cell border, you shall guarantee that the routing blockage layer has sufficient slots for routing , otherwise the router will not be able to route signal to a pin covered with blockage layer from all directions.
Also you may raise the ports up to a metal layer that is not used in your cell, in this case , you will not need to define routing blockage for this layer and the router will reach the pin freely.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
