saywhatsaywhat
Newbie level 1
VHDL errors: type error resolving infix expression "<="; Cannot read output "diff"
I've been getting this error when I compile. Could anyone help me?
# ** Error: file1.vhd(157): Type error resolving infix expression "<=".
# ** Error: file1.vhd(157): Cannot read output "diff".
# ** Error: file1.vhd(157): near "<=": expecting: ';'
I've been getting this error when I compile. Could anyone help me?
# ** Error: file1.vhd(157): Type error resolving infix expression "<=".
# ** Error: file1.vhd(157): Cannot read output "diff".
# ** Error: file1.vhd(157): near "<=": expecting: ';'
Code:
USE work.own_types.all;
-- std_logic
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
--use IEEE.numeric_std.signed;
library UNISIM;
use UNISIM.VComponents.all;
--library textutil; -- Synposys Text I/O package
-- use textutil.std_logic_textio.all;
ENTITY comparator IS PORT (
clk: in std_logic;
reset: in std_logic;
data: in std_logic_vector (0 to 31);
iv_ready: in std_logic; -- IV data sending will start from next cycle
sv_ready: in std_logic; -- SV data sending will start from next cycle
data_valid: in std_logic; -- Current input data is valid
comp_ready: out std_logic; -- The comparison result is ready
diff: out std_logic_vector (0 to 31)); -- The accumulated absolute difference
END comparator;
ARCHITECTURE behavioral OF comparator IS
constant DP_NUM :integer := 14; -- number of data points
SIGNAL diff_sum :std_logic_vector(0 to 31); -- summation of difference
SIGNAL dp_count :std_logic_vector(0 to 15); -- data point counter
SIGNAL sig_count :std_logic_vector(0 to 15); -- sigature vector counter
SIGNAL iv :std_logic_vector(0 to 31); -- iv (read from memory)
SIGNAL sv :std_logic_vector(0 to 31); -- sv (delay data)
SIGNAL comp :std_logic; -- compare enable asserted when signature vector is not 0
TYPE comparator_state IS (idle, rec_data, rec_sig, done, flush);
SIGNAL sm :comparator_state; -- state of the comparator
SIGNAL nwe :std_logic; -- not write enable for sram
SIGNAL addr :std_logic_vector(15 downto 0); -- sram address
BEGIN -- behavioral
-- This process generates the signal sv and comp.
-- When the comparator is in rec_sig state, the sv is the delayed
-- input data. If the input sv is not zero, then the comp is the
-- delayed data_valid. The one cycle delay is inserted because
-- the iv, when read out from the sram, is delayed one clock cycle.
delay_sv: PROCESS (clk, reset)
BEGIN
if reset = '1' THEN
sv <= (others => '0');
comp<= '0';
ELSIF rising_edge(clk) THEN
IF( sm = rec_sig) THEN
sv <= data;
IF (conv_integer(data) = 0) THEN
comp <= '0';
ELSE
comp <= '1';
END IF;
ELSE
sv <= (others => '0');
comp <= '0';
END IF;
END IF;
END PROCESS;
-- This process generates the signal diff_sum
-- When comp (compare enable) is 1 then diff_sum is the accumulated
-- absolute different between iv and sv
acc_diff: PROCESS (clk, reset)
BEGIN
if reset = '1' THEN
diff_sum <= (others=>'0');
ELSIF rising_edge(clk) THEN
if(comp = '1') THEN
if (sv > iv) THEN
diff_sum <= conv_std_logic_vector(conv_integer(diff_sum) + conv_integer(sv) - conv_integer(iv), 32) ;
ELSE
diff_sum <= conv_std_logic_vector(conv_integer(diff_sum) + conv_integer(iv) - conv_integer(sv), 32) ;
END IF;
ELSIF (sm = rec_data) THEN
diff_sum <= (others => '0');
END IF;
END IF;
END PROCESS;
-- This process describes the FSM of the comparator. It also generates signals
-- dp_count, sig_count and comp_ready.
-- dp_count indicates the number of IV data that have been received
-- sig_count indicates the number of SV data that have been received.
-- Please refer to the homework assignment for the detailed information of the
-- FSM.
PROCESS (clk, reset)
BEGIN
if reset = '1' THEN
sm <= idle;
dp_count <= (others=>'0');
sig_count <= (others=>'0');
comp_ready <= '0';
ELSIF rising_edge(clk) THEN
CASE sm IS
WHEN idle =>
dp_count <= (others=>'0');
sig_count <= (others=>'0');
IF iv_ready = '1' THEN
sm <= rec_data;
comp_ready <= '0';
END IF;
WHEN done =>
WHEN rec_data =>
WHEN rec_sig =>
WHEN flush => sm <= done;
WHEN others => sm <= done;
END CASE;
END IF;
END PROCESS;
-- If the comparator is in rec_data state and input data is valid, then
-- the sram write enable is asserted so that the IV data can be stored
-- in the sram
nwe <=
--
-- When the comparator is in rec_data state, the (write) address of
-- the sram is equal to dp_count. When the comparator is in the rec_sig
-- state, the (read) address of the sram is equal to sig_count.
addr(15 downto 0) <=
-- The output diff is equal to diff_sum
diff <= diff_sum;
-- SRAM 0
ram0: sram64kx8 PORT MAP(
ncs1 => '0',
cs2 => '1',
addr => addr,
data_in => data(0 to 7),
data_out => iv(0 to 7),
nwe => nwe,
noe => '0',
clk => clk
);
-- SRAM 1
ram1: sram64kx8 PORT MAP(
ncs1 => '0',
cs2 => '1',
addr => addr,
data_in => data(8 to 15),
data_out => iv(8 to 15),
nwe => nwe,
noe => '0',
clk => clk
);
-- SRAM 2
ram2: sram64kx8 PORT MAP(
ncs1 => '0',
cs2 => '1',
addr => addr,
data_in => data(16 to 23),
data_out => iv(16 to 23),
nwe => nwe,
noe => '0',
clk => clk
);
-- SRAM 3
ram3: sram64kx8 PORT MAP(
ncs1 => '0',
cs2 => '1',
addr => addr,
data_in => data(24 to 31),
data_out => iv(24 to 31),
nwe => nwe,
noe => '0',
clk => clk
);
END behavioral;