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How to design the OPAMP used in 1-bit sigma-delta modulator?

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I'm designing a 1-bit sigma-delta modulator. I find the differential voltage at the OPAMP input is greater than √2 * (VGS-VTH) at the begining of integration phase, which is caused by the big difference between input voltage and feedback voltage. As you know, this will cause slewing, and hence distortion. The big difference between input voltage and feedback voltage is inherent in a 1-bit sigma-delta modulator. My question is how to avoid the slewing? If the slewing is inevitable, what's the criteria of designing the OPAMP used in the modulator?
 

Re: How to design the OPAMP used in 1-bit sigma-delta modula

for linear transient, increase the input transconductance and the output current of opamp to increase SR.
if slewing is inevitable, a conservative method, design the opamp with enough bandwidth to settle within the overall ADC resolution. but maybe the bandwidth isn't needed so large, simulation can be used to determine it.
good luck
 

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