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SystemVerilog using DPI

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samuraign

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dpiheader

Hi
Can any body give me a script or steps to use C-code and SystemVerilog using
NcVerilog.


I am using the following script but ncsim is not taking the *.so file.
Please have a look at the script.
I am not sure whether this is the only procedure that w need to do.
If somebody knows an easy procedure or steps,please post it here.


//script starts from here:-
rm -rf INCA_libs
rm *.so
ncvlog arrays.v -sv
ncelab -dpiheader dpi.h worklib.arrays:module
gcc -g -c -fPIC -shared -o dispary.so dispary.c -I/x/y/z/IUS/5.6/solaris/tools/include
ncsim worklib.arrays:module -dispary.so -sv_root

ncsim log report:-
ncsim(64): 05.60-p001: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncsim: *F,BADOPT: unknown or ambiguous options (-dispary.so).

C-file:-(dispary.c)
#include <stdio.h>

void displayArray(char *s) {
printf("The Array Contents: %c\n",*s);
}

SV Testbench file:-arrays.v
`define DYN 6
`define MAX_SIZE 1
`define MIN_SIZE 0

module arrays;
int arrOne [`MAX_SIZE:0][`MIN_SIZE:0];
byte m[]; // Current Size will be '0'.
int i,j;
int k;

import "DPI-C" context displayArray = function void displayValue(inout byte arrVal);

initial begin
for(i=0;i<=`MAX_SIZE;i++) begin
for(j=0;j<=`MIN_SIZE;j++) begin
arrOne[j] = (i+1)*3.2*(j+1);
$display("Array 'arrOne[%0d][%0d]' is: %0d\n",i,j,arrOne[j]);
end
end
end

initial begin
$display("The Array Size is: %0d",m.size());
m = new[`DYN]; // The size is determined at run_time.
for(k=0;k<m.size();k++) begin
m[k] = (k*1) + 80; // Fill the array.
displayValue(m[k]);
end
m.delete(); // Delete the dynamic array.
$display("The new Array Size is: %0d",m.size());
end
endmodule
 

system verilog printf

samuraign said:
Hi
Can any body give me a script or steps to use C-code and SystemVerilog using
NcVerilog.


I am using the following script but ncsim is not taking the *.so file.

You may need to set LD_LIBRARY_PATH as well.
Please have a look at the script.

Code:
ncsim worklib.arrays:module -dispary.so -sv_root

ncsim log report:-
ncsim(64): 05.60-p001: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncsim: *F,BADOPT: unknown or ambiguous options (-dispary.so).

Here is the issue: The "dispary.so" is SO file and NOT an option - you should have noticed the error from NCSIM.


Here is a working example from other forum.

HTH
Ajeetha, CVC
www.noveldv.com

Code:
----file top.v--------
module top ();

import "DPI-C" context pass_string_c= task pass_string_sv(input string a);

import "DPI-C" context string_c2v_c= function string string_c2v_sv();

string some_string;

// This doesnt work in IUS583, will work in IUS6.0
export "DPI-C" print_string_c = function print_string_sv;
   
function void print_string_sv(input string aaa);  
 $display("Exported Verilog String=  %s", aaa);
endfunction

initial
  begin
  some_string = "pass it ON";
  // enable when running IUS6.0
  pass_string_sv(some_string);  // pass string to C
  $display("Verilog: %s \n", string_c2v_sv() );  // get string from C
 $finish; 
end

endmodule


Code:
-----file main_task.c-----
#include <stdio.h>
#include <svdpi.h>

// to use io_printf (prints to ncsim.log)
#include <veriuser.h>

 void pass_string_c(const char* a) {
   io_printf("DPI: %s\n", a);
   // now call exported function
   print_string_c("string passed from C");  // This wont work in IUS583
}

 const char* string_c2v_c(void) {
   io_printf("C: give up a string\n");
   return "Gimme String";
}

Code:
-----file: RUN_NC (script)------
rm -r INCA_libs
rm *.so
rm *.log
rm *.h

# Create .h file for Exported tasks/functions only 
# (imported function do NOT need .h file):
ncverilog +sv top.v +ncdpiheader+dpi.h +elaborate +ncelabargs+-messages

# ncvlog -sv top.v -mess
# ncelab top -sv  -dpiheader dpi.h -mess

gcc -fPIC -shared -o main_task.so  main_task.c  -I/`ncroot`/tools/inca/include

ncverilog +sv top.v +sv_lib=main_task.so +access+r +ncsimargs+"-sv_root ./"

----file: ncverilog.log (IUS6.02)-----------
ncsim> run
DPI: pass it ON
Exported Verilog String= string passed from C
Verilog: C: give up a string
Gimme String

Simulation complete via $finish(1) at time 0 FS + 0
./top.v:22 $finish;
ncsim> exit
 

modelsim dpi export function

I am using IUS5.6 for running the following script

//Script start
rm -rf INCA_libs
rm *.so
rm *.log
rm *.h

ncverilog +sv arrays.v +ncdpiheader+dpi.h +elaborate +ncelabargs+-messages

#ncvlog -sv arrays.v -mess
#ncelab arrays -sv -dpiheader dpi.h -mess

gcc -fPIC -shared -o dispary.so dispary.c -I/x/y/z/IUS/5.6/solaris/tools/include

ncverilog +sv arrays.v +sv_lib=dispary.so +access+r +ncsimargs+"-sv_root ./"
//script ends

The above script I am running to simulate testbench "arrays.v" which calls "dispary.c" file.
Will the above script works for running SystemVerilog with IUS5.6

I am getting the following simulation error.
//ncverilog log file starts
ncverilog(64): 05.60-p001: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
TOOL: ncverilog(64) 05.60-p001: Started on Mar 20, 2007 at 15:22:37 JST
ncverilog
+sv
arrays.v
+sv_lib=dispary.so
+access+r
+ncsimargs+"-sv_root ./"
file: arrays.v
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.arrays:v <0x5ee86587>
streams: 2, words: 911
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 1 1
Registers: 7 5
Initial blocks: 2 2
Writing initial simulation snapshot: worklib.arrays:v
Loading snapshot worklib.arrays:v .................... Done
ncsim: *W,NOLDPI: Unable to load dispary.so.
OSDLERROR: ld.so.1: ncsim: fatal: .//dispary.so: wrong ELF class: ELFCLASS32.
ncsim: *F,NOFDPI: Function displayArray not found in any of the shared object specified with -SV_LIB switch.
TOOL: ncverilog(64) 05.60-p001: Exiting on Mar 20, 2007 at 15:22:39 JST (total: 00:00:02)
ncverilog: *E,SIMERR: Error during Simulation (status 2), exiting.
TOOL: ncverilog(64) 05.60-p001: Exiting on Mar 20, 2007 at 15:22:39 JST (total: 00:00:02)
//ncverilog log file ends.

Added after 24 seconds:

I am using IUS5.6 for running the following script

//Script start
rm -rf INCA_libs
rm *.so
rm *.log
rm *.h

ncverilog +sv arrays.v +ncdpiheader+dpi.h +elaborate +ncelabargs+-messages

#ncvlog -sv arrays.v -mess
#ncelab arrays -sv -dpiheader dpi.h -mess

gcc -fPIC -shared -o dispary.so dispary.c -I/x/y/z/IUS/5.6/solaris/tools/include

ncverilog +sv arrays.v +sv_lib=dispary.so +access+r +ncsimargs+"-sv_root ./"
//script ends

The above script I am running to simulate testbench "arrays.v" which calls "dispary.c" file.
Will the above script works for running SystemVerilog with IUS5.6

I am getting the following simulation error.
//ncverilog log file starts
ncverilog(64): 05.60-p001: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
TOOL: ncverilog(64) 05.60-p001: Started on Mar 20, 2007 at 15:22:37 JST
ncverilog
+sv
arrays.v
+sv_lib=dispary.so
+access+r
+ncsimargs+"-sv_root ./"
file: arrays.v
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.arrays:v <0x5ee86587>
streams: 2, words: 911
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 1 1
Registers: 7 5
Initial blocks: 2 2
Writing initial simulation snapshot: worklib.arrays:v
Loading snapshot worklib.arrays:v .................... Done
ncsim: *W,NOLDPI: Unable to load dispary.so.
OSDLERROR: ld.so.1: ncsim: fatal: .//dispary.so: wrong ELF class: ELFCLASS32.
ncsim: *F,NOFDPI: Function displayArray not found in any of the shared object specified with -SV_LIB switch.
TOOL: ncverilog(64) 05.60-p001: Exiting on Mar 20, 2007 at 15:22:39 JST (total: 00:00:02)
ncverilog: *E,SIMERR: Error during Simulation (status 2), exiting.
TOOL: ncverilog(64) 05.60-p001: Exiting on Mar 20, 2007 at 15:22:39 JST (total: 00:00:02)
//ncverilog log file ends.


I have set LD_LIBRARY in my ncverilog setup file.
Any idea about the above error.
 

dpi ncsim

Hi,

samuraign said:
I am using IUS5.6 for running the following script

I am getting the following simulation error.
//ncverilog log file starts
ncverilog(64): 05.60-p001: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
TOOL: ncverilog(64) 05.60-p001: Started on Mar 20, 2007 at 15:22:37 JST

So you are running 64-bit version on a 64 bit machine.

Loading snapshot worklib.arrays:v .................... Done
ncsim: *W,NOLDPI: Unable to load dispary.so.
OSDLERROR: ld.so.1: ncsim: fatal: .//dispary.so: wrong ELF class: ELFCLASS32.

Your gcc and hence the SO file is 32 bit.

Try using 32 bit NC first. Do you really need 64 bit for this?

Regards
Ajeetha, CVC
www.noveldv.com
 

modelsim svdpi.h

Thank U, problem is solved.

Exploring more on System Verilog DPI(modelsim etc...).
 

using dpi

Hi ,

I am using the above script for running co-simulation(C-code & SystemVerilog).
But I am not able to get my waveform file.

Lines written in testbench to dump wave.
-----------------------
initial begin
$recordfile("./wave/TD_TST.trn");
$recordvars;
end
-----------------------

Script to run System Verilog
------------------------------
rm -rf INCA_libs
rm *.so
rm *.log

ncverilog +sv flist +ncdpiheader+dpi.h +elaborate +ncelabargs+-messages

gcc -fPIC -shared -o TD.so TD.c -I/x/y/z/IUS/5.6/solaris/tools/include

ncverilog +sv flist +sv_lib=TD.so +access+rcw +ncsimargs+"-sv_root ./"

Error message while running NCverilog
---------------------------------------------
ncsim> run
ncsim: *internal* (ssl_shm_add_scope - not a scope).
Observed simulation time : 0 FS + 0
Please contact Cadence Design Systems about this problem
and provide enough information to help us reproduce it.
***Current stack trace:
-->[Don't Know ] 0 <don't know>
-->[Don't Know ] 5d62b0 ncdbg_exit + 1bdc
-->[Don't Know ] 3eb568 sss_tag_dbend + 520
-->[VPI Overhead ] 136a3c vpi_tag_ostart + 191b4
-->[VPI Overhead ] 136afc vpi_tag_ostart + 19274
-->[VPI Overhead ] 1385a8 vpi_tag_ostart + 1ad20
-->[VPI Overhead ] 156f68 vpi_tag_ostart + 396e0
***Verilog source where error occurs:
$recordfile(...) (PLI calltf)
Module: TD_TST
Instance: TD_TST
File: ./TD_TST.v
Line: 422
ncverilog: *E,SIMERR: Error during Simulation (status 255), exiting.
---------------------------------------------------------------------------------
 

modelsim dpi

OSDLERROR , any clue on this ?

unable to load *.so file. what could be the problem ?
 

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