When to use a 50% Duty Cycle in electronic applications

50% duty cycle

why do we generally use 50% duty cycle i.e 50% high and %50%low?
Can we use other values?
Wht will be the effect of using other %age

Re: 50% duty cycle

of course we can use other choices, it depends on your applications.

Re: 50% duty cycle

engrbabarmansoor said:

why do we generally use 50% duty cycle i.e 50% high and %50%low?
Can we use other values?
Wht will be the effect of using other %age

Click to expand...

For application like a PLL XOR phase detector, it will not work correctly unless you use a 50% duty cycle inputs..

Cheers,
-- Knack

Re: 50% duty cycle

knack said:

engrbabarmansoor said:

why do we generally use 50% duty cycle i.e 50% high and %50%low?
Can we use other values?
Wht will be the effect of using other %age

Click to expand...

For application like a PLL XOR phase detector, it will not work correctly unless you use a 50% duty cycle inputs..

Cheers,
-- Knack

Click to expand...

maybe it will work if the duty cycle of the input square wave isn't 50% for XOR PD, i think.

50% duty cycle

In ASIC design point of view, if ur design is using single-edge triggered. Then, it should'nt be a problem.

As long as you leave enough time for the data
to stabilize at the edge triggered...meet ur setup n hold time. I would say ur design should be fine.

Unless, u r using both clock edges. One of ur cycle would be a disadvantage.

Hope it helps

Re: 50% duty cycle

engrbabarmansoor said:

why do we generally use 50% duty cycle i.e 50% high and %50%low?
Can we use other values?
Wht will be the effect of using other %age

Click to expand...

I have the similar question: In Which Situations should We Apply A 50% Duty Cycle Clock?

Re: 50% duty cycle

DZC said:

engrbabarmansoor said:

why do we generally use 50% duty cycle i.e 50% high and %50%low?
Can we use other values?
Wht will be the effect of using other %age

Click to expand...

I have the similar question: In Which Situations should We Apply A 50% Duty Cycle Clock?

Click to expand...

i'm designing a SC sigma-delta modulator which uses two non-overlap clocks, in general, they use 50% duty cycle (approximately)

50% duty cycle

We Apply A 50% Duty Cycle Clock when the clock is used for ADC.

Re: 50% duty cycle

A 50% duty cycle squarewave signal has no even harmonics.

Re: 50% duty cycle

One of the possible reasons may be to avoid hold or setup violations if we are using +ve as well as -ve edge triggered Flops in our design. well it is just my guess. I may stand corrected please.
Cheers

Re: 50% duty cycle

50% duty cycle square wave has no even harmonics.. so what? not that important (if true..). non-overlap clocks are everywhere you look.

50% duty cycle square wave has ZERO dc (avg) value, and that's more important. put capacitive coupling and see why.

Re: 50% duty cycle

ch1k0 said:

50% duty cycle square wave has no even harmonics.. so what? not that important (if true..).

Click to expand...

In some applications, it is very important not to have even harmonics in the excitation signal.
An example is when you detect a signal at the second harmonic of the excitation.

Re: 50% duty cycle

Could you give example of application where you want detect signal exactly on top of second harmonic of clock signal ?
could you explain why periodic signal 50% duty cycle show no second harmonic, and periodic 75% duty cycle has?

50% duty cycle

1. Any sensor that has a purely odd transfer characteristic for a zero signal and not purely odd characteristic for non-zero signal translates the signal frequency to the frequency of the even harmonics of the ac excitation. An example is fluxgate, but there also are many other sensors and experiments, especially in physics, where detection on even harmonics is very efficient.

2. Think of sinc.

Re: 50% duty cycle

ch1k0 said:

could you explain why periodic signal 50% duty cycle show no second harmonic, and periodic 75% duty cycle has?

Click to expand...

50% duty cycle

sorry but how to get two non-overlapping clocks each of 50% duty cycle !!!!!

Re: 50% duty cycle

depending on the application ; you can judge if certain duty cycle can make a problem or not, but generally , very low duty cycle means you didnt benefit from the low frequency you operate at, for example , if you make a divider in a PLL, this divider output will be an input to the PFD, and so , if your divider divide for example from 1 GHz to 50 MHz, then if your output duty cycle very low, then you want the PFD to work at a higher frequency than 50 MHz, i.e. to follow the narrow pulse and not miss it,so you may put acceptable range for your duty cycle, and so on

50% duty cycle

Most of the times 50% duty cycle is needed like clock signals where high and low durations equally long and so minimal clock period can be used based on maximum circuit delay during high or low duration. Also in any case it is important to know what is the duty cycle so that one can make sure longest circuit delay in high and low duration is within the duration (think of asynchronous logic applications with different delays on high and low clock durations).

Now there are infinity of concerns in circuit design and as wisely mentioned by others second harmonics. average value etc. also comes into picture depending on application.

What is important is to know what is going to be accomplished -- not blindly copying circuits from books or others and thinking that one is doing a design is asking for trouble for sure Uncertainties, unique problems raises questions and requires unique solutions which make designing a fun job.

In my circuits time to time I change the duty cycle to minimize the period so things can be done faster but this all depends on what I am doing. In short if clock is 50% it is easier to generalize the thinking process and attend overall higher level circuit issues. Some circuits particularly where rise time and fall time well balanced (synchronous logic circuits) greatly benefit 50% percent duty cycle clocks by worrying less of duty cycle