Successive Approximation ADC with bits > 12

Did anyone have experience to design more than 12bits SAR?
I am scratching my head to achieve this beyond 10 bit.
Typically 10bits is easy to achieve without much calibaration.
However, beyond than this is not easy.

What exactly are the problems that you're facing ?

My problem is how to design SARADC with more than 12bits,
since capacitive array mismatch is killing, calibration for this is difficult and i have no idea how to achieve that even in simulation

12b should be ok without calibration. More than 12b is what: 13b? 16b? 200b?

What is the segmentation you're using?

I am using 6C-Cc-6C split array and you know, running through 4096 steps in transient simulation to check INL/DNL is taking much time and some faster simulator is required, like HS*M or Nanos*m, from those simulators, it's not easy to get perfect results and that's why I said, even not good in simulation. if on the other hand, simulate with a 1Khz sine wave to get SNR maybe a good choice.

What have u done for your ADC? Let's share

Did u play around more than 12b? I mean 14b or 16b, Not more than 16b for SARADC as it is not quite useful for applications, if more than 16b, I prefer SDADC since it is much standardized and easier compare to 16b SARADC without much literatures talking about how to do that?

What kind of comparators you did use in your design ?

Having "not perfect" results in HS*M or Nanos*m is normal. What you should do in these simulators is verify functionality. Even if you could run accurate SPICE simulations to get INL/DNL, you would have to do several monte-carlo runs.

INL/DNL must be inferred from the simulations of the blocks that cause code transition level variations (cap array in your case) and, eventually, from behavioral models of the ADC made, for example, in MATLAB.

Regards

Do u mind sharing your design experience?
i mean more detailed description since I always would expect
someone here can share design experience with me, instead of just
a superficial discussion. Much thanks

Regarding SAR ADCs, I've designed up to 12b.

Hey, maxwellequ

Share with us more on the real design.
How did you work out with that?
Any tricks you have done? i really want to have chance with share real design experience with some of you here online, instead of just commenting all those questions that can have answers from books, those to me, are useless actually.

For 12b ADC, I come up with some variable clock cycle to tackle the INL/DNL issue during conversion.

hi maxwellequ

Any comment?

What you're requesting is confidential information :| . If I see someone with particular doubts and I see that I can answer, then I do. More than that, I cannot disclose, as you surely understand.

Moreover if you can find the answers for particular question in books, why do you ask them here ?

Regards

Most of the questions I asked were not easily have answers from books, or books that I don't have ..haha..
Hey, I disclose some of my secrets here, when i design the 12b SAR, I tried to do variable clocking to have different conversion rates for each bit. That helps more accuracy.