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Verilog While loop,For loop is synthesisable????

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for loop in verilog

ofcourse they are if u write them in a way they should be
one simple clue is
do not include delay in the loops as delays won't be synthesisable
 

verilog for loop synthesis

For(i=0,i< 10,i++)
I think this works.....
where as this......
For(i=0,i<k,i++)
where k is a variable.........changes during simulation.....
I dont think it will be synthesisable........

Comments please.....
 

for loop verilog

ankit12345 said:
For(i=0,i< 10,i++)
I think this works.....
where as this......
For(i=0,i<k,i++)
where k is a variable.........changes during simulation.....
I dont think it will be synthesisable........

Comments please.....
Click to expand...

it is sure that your code is NOT synthesizable.

another thing: how do you think it maybe synthesizable??? what happen if k=99999999999999999999999999?
I think you are missing the significant hardware concepts.
 

verilog loop

Yes !!
For loop is synthesizable only if "k" is constant variable ..
number should be restricted to 32bit value !! or v must defined variable length 32bit or 64bit while declaring ...
 

verilog for

Yes ,

It will Synthesizable if and only if 'k' should be constant
 

verilog while

the for loop and while loop are dependent on the type of design libaraires u r using to hem
i mean fpga
 

for loop verilog synthesis

It is synthesizable but it is always advised that for loops are not to be used in RTL coding. This is because it consumes lot of resources (like area etc.etc) . However u can use it in behavioral coding becuse we do not synthesize behavioral codes.
 

verilog for loop syntax

In verilog,synthesizable of for loop and while loop depends on which tools you are using .

But it is better dont use it in RTL because it reflects replica of hardware.
 

verilog synthesizable for loop

using of loops (for and While) consumes lot hardware and the then arises overall frequency loss. hence it is advisable to avoid for loops in RTL coding. and the synthesis tool also plays a mojor role.
 

is for loop synthesizable

for Verilog HDL, as its name says, is a language to discribe a circuit. so you can't depend on the synthesise tool to generate your circuit before you design the circuit itselfe.
such as the code
For(i=0,i<k,i++)

have you seen such circuit? if you have not, how could you ask a mathine to generate a circuit for you?
 

verilog loop synthesis

actually for loop is synthesizable because we are mentionong the constat that is the end of loop for (1=0;i<=10;i++)

but in case of the while it is dynamic; ex: while(i<k)
we dont know the value of k
if u give constant it is synthesised .


ankit12345 said:
r not??????
Click to expand...
 

verilog for loops

anilkumarv said:
It is synthesizable but it is always advised that for loops are not to be used in RTL coding. This is because it consumes lot of resources (like area etc.etc) . However u can use it in behavioral coding becuse we do not synthesize behavioral codes.
Click to expand...


Anil Kumar, Can u tell how the resources increase by using looping conditions
 

for loops in verilog

Clearly one has to be careful to make for loops synthesizable (essentially make sure that loop termination is set on some constant).
I would take issue that they "should not be used"... ostensibly because they "consume excessive area". They have their place in simplifying coding. An example would be performing edge detection on an array of values, for example:

integer i;

always @(posedge clk)
begin
for (i=0,i<NUMBER_OF_PORTS,i=i+1)
begin
port_was <= port_is;
if (port_was == 1'b0 && port_now == 1'b1)
port_edge_hi_detected <= 1'b1;
else
port_edge_hi_detected <= 1'b0
end
end

Note that the always @ statement can NOT be inside the FOR loop.
This is a convenient coding style. It consumes no more logic than if I had cut and pasted copies of the clauses... AND... it allows the constant to be a parameter, so the code can expand/collapse for particular usages. NUMBER_OF_PORTS has to resolve to a constant at compile time.

These days, any synthesis tool worth anything should handle this type of usage with no problem.
 

loop in verilog

The simple thing is that if u are able to think the implementation then synthesis engine can also think :)
 

verilog for loop example

I have a similar question about for loops.
Let's say i write:
Code: 
begin
 for(i=0;i<7;i=i+1)
 begin
    mem[i+1]=mem[i];
 end
 mem[7]=0;
end

is this synthesizable??
Is it certain that all the statements are going to be executed sequentialy and NOT concurrently??
Is it FPGA dependent?

Thanks.
 

verilog loops

This is synthesisable, but not useful code when using blocking assignment. It has the effect of copying mem[0] to mem[1] .. mem[6] and zeroing mem[7]. A HDL loop is never "executed sequentially", it is evaluated sequentially but executed in parallel.

Using nonblocking "<=" assignment, the code would basically form a shift register, which sounds more meaningful to my opinion. Overwriting of mem[7] would still occur, however.
 

for loop synthesis in verilog

FvM said:
This is synthesisable, but not useful code when using blocking assignment. It has the effect of copying mem[0] to mem[1] .. mem[6] and zeroing mem[7]. A HDL loop is never "executed sequentially", it is evaluated sequentially but executed in parallel.

Using nonblocking "<=" assignment, the code would basically form a shift register, which sounds more meaningful to my opinion. Overwriting of mem[7] would still occur, however.
Click to expand...

in VLDH can be rewritten as:
...
for i in 0 to 6 loop
mem[i+1] <= mem;
end loop;
mem[0] <= 1'b0;
...
 

for loop in verilog code

OK so understand that only during simulation this is going to be executed sequentially unless i use a nonblocking assignment.

correcting my code so that overwriting mem[7] makes sense... :)
Code: 
begin
 output<=mem[0];
 for(i=0;i<7;i=i+1)
 begin
    mem[i]<=mem[i+1]; //changed sides
 end
 mem[7]<=8'b00000000;
end

So can i be sure now that they are going to be executed sequentially?

Thanks a lot guys!
 

is for loop synthesizable in verilog

loops are synthesisable with generate statement
 

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