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question about MOS CML circuit

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bageduke

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pmos based cml

When we design MOS current mode logic, do we have to design all switching NMOS in saturation region? If yes, then when we deal with two cascoded NMOS transistors, we have to level shift bottom input down a little bit in order to keep both transistors in saturation, otherwise, the bottom one will stay in triode mode. Am I right?
 

level shifter cml

bageduke said:
When we design MOS current mode logic, do we have to design all switching NMOS in saturation region? If yes, then when we deal with two cascoded NMOS transistors, we have to level shift bottom input down a little bit in order to keep both transistors in saturation, otherwise, the bottom one will stay in triode mode. Am I right?
Click to expand...
hi,
can you post your ckt to describe the question more clearer,right?
jeff
 

cml circuit

Sorry about it.

I don't have specific ckt. but here I post one MCML gate.

As I know, the transistor of RFN needs to be in saturation as current source; and the transistor of RFP needs to be in triode as resistor. But how about those switching transistors of A, B, C? Do they have to be in saturation?

If the answer is yes, I become confused. Because signals A, B, C could also come from other MCML gates and they are supposed to have same voltage swing and common voltage level. For example, if A, B, C are all logic H(VDD), then the transistors of A and B are definitely in triode mode, right?

so if we want to keep transistors of A, B, C all in saturation, we have to use level shifter to shift A and B's level down. Am I correct?

Or, those switching transistors don't need to be in saturation.

Anyone can give me an answer? Thanks a lot.
 

Anyone has any idea? Or I didn't discribe my question clearly.

Thank you for any inputs!
 

bageduke said:
Sorry about it.

I don't have specific ckt. but here I post one MCML gate.

As I know, the transistor of RFN needs to be in saturation as current source; and the transistor of RFP needs to be in triode as resistor. But how about those switching transistors of A, B, C? Do they have to be in saturation?

If the answer is yes, I become confused. Because signals A, B, C could also come from other MCML gates and they are supposed to have same voltage swing and common voltage level. For example, if A, B, C are all logic H(VDD), then the transistors of A and B are definitely in triode mode, right?

so if we want to keep transistors of A, B, C all in saturation, we have to use level shifter to shift A and B's level down. Am I correct?

Or, those switching transistors don't need to be in saturation.

Anyone can give me an answer? Thanks a lot.
Click to expand...

It seems A,B,C are just digital switches, they have 2 states: on/off, no need in saturation. all inputs should be logic level.
RFN limites the leakage when gate turns over.
 

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