About a Two-stage op amp

how to simulate open loop gain

In order to simulate AC response of a two stage op amp,I designed a two stage op amp according to Allen book CMOS Analog Circuit Design fig6.3-3....

But,while .op analyse with Hspice,I found the voltage between drain and source of M7 is so small....

Actually,I designed it according to Allen book's example 6.3-1 ,and simulated with TSMC.35 tec....

who can help me??

Thanks in advance!

Are you sure about the biasing? How is the first stage doing?

You might have a systematic offset?

One quick check, short the output to the negative terminal and the positive terminal to whatever common mode you expect to see at the output, then run .op again.

Thanks ,jonashat...
Actually last time I havd shorten the output to negtive terminal,and found that all mos transistor are in saturation region. Foremore,if I connect the output and negtive teminal with a large resistance,for example,20MEGOHM,and all mos transistor are also in saturation.

Of course,I give the positive teminal a bias about 1.8v....But I think all transistor should in saturation
region without the feedback resistance or short wire.

Is that right?

That sounds right..
I think that leaves us with the systematic offset issue.

You need to resize your transistors to satisfy the following:

W4/(0.5 * W5) = W6/W7

And in your case, you're way off this relation

You said that you have followed P. Allen's book, I don't remember if he actually talked about systematic offset, but regardless this relation should be satisfied.

jonashat said:

That sounds right..
I think that leaves us with the systematic offset issue.

You need to resize your transistors to satisfy the following:

W4/(0.5 * W5) = W6/W7

And in your case, you're way off this relation

You said that you have followed P. Allen's book, I don't remember if he actually talked about systematic offset, but regardless this relation should be satisfied.

Click to expand...

Thanks,jonashat...
Someone told me to reduce the ratio of (W/L)7,so I adjusted the over-voltage of M3,4 form 0.4v to 0.25V...Then resized most of the transistors . Now ,the circuit work well while .op analyse.....

After receiving you reply,I found the new design satisfy the relation of your reply...I have never seen this equation before.Where does it come from?

Another problem is how to simulate open-loop gain with Hspice??
According to Allen book,I connected a large resistance between out and in-,and a large capacitance from in- to gnd....But the curve is not good at all.
And I set as follow:

**************
xop1 vdd gnd in- in+ out twostage_ac

Vin1 in+ gnd dc 1.8 ac 1
R out in- 20gohm
C in- gnd 0.01

.ac dec 10 1 10meg
.print ac vdb(out) vp(out)
.probe
.end
*******************

Is there anything wrong?

Added after 8 minutes:

Of course,if I modify the stop Fre. from 10meg to 2k...
then I can get a curve,and it looks good...

But I think it is not the answer....

What about you opinion??

8k-rom said:

After receiving you reply,I found the new design satisfy the relation of your reply...I have never seen this equation before.Where does it come from?

Click to expand...

I think you can find in some analog design books like Grey and Meyer or Johns and Martin. Just look for systematic offset and you should get a very similar equation. It basically tells you that since M5 and M7 are scaling the currents with a certain ration and since M4 and M6 have the same Vgs, then M4 and M6 should be sized to maintain the same current density.

8k-rom said:

Another problem is how to simulate open-loop gain with Hspice??
According to Allen book,I connected a large resistance between out and in-,and a large capacitance from in- to gnd....But the curve is not good at all.
And I set as follow:

**************
xop1 vdd gnd in- in+ out twostage_ac

Vin1 in+ gnd dc 1.8 ac 1
R out in- 20gohm
C in- gnd 0.01

.ac dec 10 1 10meg
.print ac vdb(out) vp(out)
.probe
.end
*******************

Is there anything wrong?

Added after 8 minutes:

Of course,if I modify the stop Fre. from 10meg to 2k...
then I can get a curve,and it looks good...

But I think it is not the answer....

What about you opinion??

Click to expand...

1. Scale the x-axis in a logarithmic scale, so that everyone can see it clearly.
2. Simulate till gain is 0dB. (I want to see the unity gain frequency)
3. What is the gm of the input diff pair and what's the load cap that you're driving?

1. Scale the x-axis in a logarithmic scale, so that everyone can see it clearly.
2. Simulate till gain is 0dB. (I want to see the unity gain frequency)
3. What is the gm of the input diff pair and what's the load cap that you're driving?

Click to expand...

Actually,I don't know how to set the x-axis in log scale previously....

Maybe I have got the answer....Because I have not set the X-axis,the curve looks
not good at all....

Thanks!!

The figure in this attachment looks nice now.

putting ur mouse right click x-axis u can choose logarithmic scale