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How to test FPGA VHDL LCD code?

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aria62

aria62

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dear friends
i've written a driver for a graphic LCD using VHDL.is there any simulator to test if the code works correctly on the LCD?i mean a simulation environment with LCD.
i've already test the code in Quartus and there is no error.

regards
 

fpga counter lcd

In order to simulate your code for LCD you need to write LCD behavioural model and then test it.
 

code fpga lcd

how did you tested without test bench??
 

lcd gui simulator

dear friends
i said i wrote the code and simulated it by means of Quartus simulator.but quartus simulator only has a waveform area . i need a software which workes like as Proteus which has a graphic environment that you can choose your LCD and place it in circuit and test the operation of your program.

regards
 

lcd fpga

if u have multisim,then u can import a vhdl model into a newly created component instead of writing a spice netlist....u can then use this model just like any other component of multisim..
 

fpga lcd code

write a model for the LCD and then test it like "vibhute_r_p" said
 

    aria62

    aria62

    Points: 2
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how to add a lcd to a fpga

If you are working with modelsim then you can create LCD model in tcl/tk
that will give you LCD gui.
 

    aria62

    aria62

    Points: 2
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fpga components in multisim

Dear nand_gates
i've never used tcl scripting language before.i studied the Quartus help for tcl but didn't see anything about LCD gui. is the modelsim tcl somthing different?would you please give me some examples or a little more explanation?

regards
 

graphic lcd simulator

again, using Modelsim you can write behavior model of your LCD and simulate i.e to see the timing
 

lcd-emulator testen

here is an example for seven segment animation in modelsim.
sevenseg.tcl
Code: 
# trace the seven segment value
when {/counter/cout} {set ss [exa -bin {/counter/cout}]}

# set ss "0000000"

set flag_ss 0

# Resize the entire canvas by a scale 
proc rescale {cvn factor} {
	global SCALE
	
	# rescale all the boxes 
	$cvn scale all 0 0 $factor $factor
	
	# rescale the text widths, too
	foreach i [$cvn find all] {
		if {[expr ! [string compare "text" [$cvn type $i]]]} {
			set t [$cvn itemcget $i -width]
			set t [expr $t * $factor]
			$cvn itemconfigure $i -width $t
		}
	}
	
	# resize the canvas itself 
	set t [$cvn cget -width]
	$cvn configure -width [expr $t * $factor]
	set t [$cvn cget -height]
	$cvn configure -height [expr $t * $factor]
}	

catch {destroy .sevenseg}
set ss_w [toplevel .sevenseg]

set fr1 [frame $ss_w.fr1]
set fr2 [frame $ss_w.fr2]

set ss_cv [canvas $fr1.ss_cv -height 20 -width 10]

$ss_cv create text 1 1 -anchor nw -fill black -text "SEVEN SEG" -width 15

set ss_a [$ss_cv create line 3 5 7 5 -fill gray -width 0] 
set ss_b [$ss_cv create line 7 6 7 10 -fill gray -width 0]
set ss_c [$ss_cv create line 7 12 7 16 -fill gray -width 0]
set ss_d [$ss_cv create line 7 17 3 17 -fill gray -width 0]
set ss_e [$ss_cv create line 3 16 3 12 -fill gray -width 0]
set ss_f [$ss_cv create line 3 10 3 6 -fill gray -width 0]
set ss_g [$ss_cv create line 4 11 6 11 -fill gray -width 0]
button $fr2.close -text "Close" -command {destroy .sevenseg; set flag_ss 0}

rescale $ss_cv 8
# indicate the existence of seven segment window
set flag_ss 1

# call the ss_monitor procedure with dummy parameters 
# I am calling this function bcos if user invokes the seven segment after the value is written 
# to it, then ss_monitor procedure is not called and seven segment LEDS remain inactive
# ss_monitor 1 2 3

pack $ss_cv
pack $fr2.close
pack $fr1
pack $fr2


trace variable ss w ss_monitor

proc ss_monitor {name arrayindex op} {
	global flag_ss ss_a ss_b ss_c ss_d ss_e ss_f ss_g ss ss_cv
	if {$flag_ss==1} {
		if {[string index $ss 0]==1} {
			$ss_cv itemconfigure $ss_a -fill blue -width 3
		} else {
			$ss_cv itemconfigure $ss_a -fill gray -width 0
		}
		if {[string index $ss 1]==1} {
			$ss_cv itemconfigure $ss_b -fill blue -width 3
		} else {
			$ss_cv itemconfigure $ss_b -fill gray -width 0
		}
		if {[string index $ss 2]==1} {
			$ss_cv itemconfigure $ss_c -fill blue -width 3
		} else {
			$ss_cv itemconfigure $ss_c -fill gray -width 0
		}
		if {[string index $ss 3]==1} {
			$ss_cv itemconfigure $ss_d -fill blue -width 3
		} else {
			$ss_cv itemconfigure $ss_d -fill gray -width 0
		}
		if {[string index $ss 4]==1} {
			$ss_cv itemconfigure $ss_e -fill blue -width 3
		} else {
			$ss_cv itemconfigure $ss_e -fill gray -width 0
		}
		if {[string index $ss 5]==1} {
			$ss_cv itemconfigure $ss_f -fill blue -width 3
		} else {
			$ss_cv itemconfigure $ss_f -fill gray -width 0
		}
		if {[string index $ss 6]==1} {
			$ss_cv itemconfigure $ss_g -fill blue -width 3
		} else {
			$ss_cv itemconfigure $ss_g -fill gray -width 0
		}
	}
}

VHDL code for counter and sevenseg decoder
counter.vhd
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
  
  port (
    clk   : in  std_logic;
    reset : in  std_logic;
    cout  : out std_logic_vector(6 downto 0));

end counter;

architecture behave of counter is
signal cout_int : std_logic_vector(3 downto 0);
begin  -- behave
  with cout_int select   --       abcdefg
  cout <= "1111110" when "0000",
          "0110000" when "0001",
          "1101101" when "0010",
          "1111001" when "0011",
          "0110011" when "0100",
          "1011011" when "0101",
          "1011111" when "0110",
          "1110000" when "0111",
          "1111111" when "1000",
          "1111011" when "1001",
          "1110111" when "1010",
          "0011111" when "1011",
          "1001110" when "1100",
          "0111101" when "1101",
          "1001111" when "1110",
          "1000111" when "1111",
          (others => 'X') when others;

  process (clk, reset)
  begin  -- process
    if reset = '0' then                 -- asynchronous reset (active low)
      cout_int <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      cout_int <= cout_int + 1;
    end if;
  end process;

end behave;

Here is how you simulate

Code: 
vlib work
vcom counter.vhd
vsim counter
source sevenseg.tcl
orce -freeze sim:/counter/clk 1 0, 0 {5 ns} -r 10
force -freeze sim:/counter/reset 0 0
run 10
force -freeze sim:/counter/reset 1 0
run 10
run 10      
run 10
run 10
 

    aria62

    aria62

    Points: 2
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Re: FPGA LCD simulator?

thank you so much
it was really interesting.i saw the 7segment GUI but still there is some errors in this part in the last code :

vlib work
vcom counter.vhd
vsim counter

Quartus doesn't recognize "vlib" and "vcom" and "vsim" as a keyword.should i replace these with somthing else?it doesn't recogmize "when" as a keyword in the first code as well.
 

FPGA LCD simulator?

it is model sim commands not quartus
 
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    aria62

    aria62

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