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Verilog function are synthesizable as we don't use timing constraint there.
Verilog Task may or may not be synthesizable depending upon your use for timing constaraint
Thanks
Anmol
Added after 23 seconds:
anmolvlsi13 said:
Verilog function are synthesizable as we don't use timing constraint there.
Verilog Task may or may not be synthesizable depending upon your use for timing constaraint
Thanks
Anmol
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