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problem on using cadence stability(stb) analysis

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eejli

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stb cadence

I have a opamp with an RC feedback. I am checking its common mode stability using stb function. It turns out there are two loops in the common mode path and stb returns me an unstable result which may result from the tail current source finite output impedance.

The question is how I can know the stb's conclusion that the loop is not stable is right? Since the differential path stability is very good.

when I use the stb function do I need to beak the loop or just put the iprobe in serial with the loop without breaking the loop.

Thanks.
 

stb法 cadence

So far as I know, you do not need to break the loop.

If the CMFB loop is unstable then this is a problem that you should solve. you cannot have a functional opamp with oscillatory common mode
 
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    eejli

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    lightgo

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analyste stb cadence

you can use ac analysis , and use big LC to break the loop at high frequency.
 

cadence stb

For multi-loop stability analysis, you should check the inner loop first and the outer loop check later.

so in your case you should make sure the CMFB has enough of phase margin, then proceed to the RC feedback path.

Hope this helps

Regards,
Smart
 
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