jimjim2k
Advanced Member level 3
leon-1 vhdl
Hi
LEON is a synthesisable VHDL model of a 32-bit SPARC* compatible processor, developed by the European Space Agency (ESA) for future space missions. To promote the SPARC architecture and enable development of system-on-a-chip (SOC) devices using SPARC cores, ESA is making the full source code freely available under the GNU LGPL license.
LEON was initially developed by Jiri Gaisler while working for ESA, and Gaisler Research is now working under ESA contract to maintain and further enhance the model. Several FPGA implementations of LEON have been demonstrated, and the first ASIC prototypes were manufactured and successfully tested by Atmel-Nantes. The processor has been extensively tested against the SPARC V8 architecture manual and the IEEE-P1754 (SPARC) standard, but have not been formally tested and certified by SPARC international as being SPARC V8 compliant.
The VHDL model is fully synthesisable and contains synthesis scripts for Exemplar Leonardo 1999.x, Synopsys FPGA-Compiler, Synopsys-DC and Synplify . Targeting a 0.35 um CMOS process (gate-array or std-cell), approximately 100 MHz can be reached with a gate count of less than 30 Kgates. The processor also fits in an ******* FPGA or Xilinx XCV300 .
1. h**p://www.estec.esa.nl/wsmwww/leon/
2. h**p://www.gaisler.com/leon.html
3. h**p://www.klabs.org/richcontent/software_content/software_and_ip_page.htm
* -> t
tnx
26-03-2002
Edited by Super Moderator
For info about ***** contact the poster.
Do it only by e-mail.
Hi
LEON is a synthesisable VHDL model of a 32-bit SPARC* compatible processor, developed by the European Space Agency (ESA) for future space missions. To promote the SPARC architecture and enable development of system-on-a-chip (SOC) devices using SPARC cores, ESA is making the full source code freely available under the GNU LGPL license.
LEON was initially developed by Jiri Gaisler while working for ESA, and Gaisler Research is now working under ESA contract to maintain and further enhance the model. Several FPGA implementations of LEON have been demonstrated, and the first ASIC prototypes were manufactured and successfully tested by Atmel-Nantes. The processor has been extensively tested against the SPARC V8 architecture manual and the IEEE-P1754 (SPARC) standard, but have not been formally tested and certified by SPARC international as being SPARC V8 compliant.
The VHDL model is fully synthesisable and contains synthesis scripts for Exemplar Leonardo 1999.x, Synopsys FPGA-Compiler, Synopsys-DC and Synplify . Targeting a 0.35 um CMOS process (gate-array or std-cell), approximately 100 MHz can be reached with a gate count of less than 30 Kgates. The processor also fits in an ******* FPGA or Xilinx XCV300 .
1. h**p://www.estec.esa.nl/wsmwww/leon/
2. h**p://www.gaisler.com/leon.html
3. h**p://www.klabs.org/richcontent/software_content/software_and_ip_page.htm
* -> t
tnx
26-03-2002
Edited by Super Moderator
For info about ***** contact the poster.
Do it only by e-mail.