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how to reduce the EMI in IC design level ?

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hutaoreal

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who knows how to reduce the EMI at IC design level , especially in digital design,and not at board level ? how to reduce EMI in circuit design?
thanks.
 

hutaoreal said:
who knows how to reduce the EMI at IC design level , especially in digital design,and not at board level ? how to reduce EMI in circuit design?
thanks.

you can use top and bottom layers as ground layer.
 

Use SSC circuit to spread to spectrum of system clock.
 

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