Assura 313 LVS error - parameter mismatches

matched layout and schematic (such as simple invertor) cannot pass the LVS check

*******************************************************************************
****** invertor schematic test018 <vs> invertor layout test018
*******************************************************************************

Filter Statistics
================= Original Filtered
Cell/Device schematic layout schematic layout
(nmos2v, N) MOS 1 1 1 1
(pmos2v, P) MOS 1 1 1 1

Reduce Statistics
================= Filtered Reduced
Cell/Device schematic layout schematic layout
(nmos2v, N) MOS 1 1 1 1
(pmos2v, P) MOS 1 1 1 1

Match Statistics
================ Total Unmatched
Cell/Device schematic layout schematic layout
(nmos2v, N) MOS 1 1 0 0
(pmos2v, P) MOS 1 1 0 0
------ ------ ------ ------
Total 2 2 0 0

Match Statistics for Nets 4 4 0 0

=====================================================================[invertor]
====== Parameter Mismatches for Instances =====================================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 1)
Schematic Instance: NM0 nmos2v
Layout Instance: avD676_1 N

w 2e-06 vs 2e-06 differs by 2.52476e-07%
l 1.8e-07 vs 1.8e-07 differs by 3.79118e-07%

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 2)
Schematic Instance: M1 pmos2v
Layout Instance: avD733_1 P

w 4e-06 vs 4e-06 differs by 2.52476e-07%
l 1.8e-07 vs 1.8e-07 differs by 3.79118e-07%

=====================================================================[invertor]
====== Summary of Errors ======================================================
===============================================================================

Schematic Layout Error Type
--------- ------ ----------
2 2 Parameter Mismatches for Instances

assura compare.rul tolerant

Hello,


In the Runset (rule) file there is a part where are described tolerancies for al devices. You must check there and to change with a proper value.

Example:
**************************
compareParameter( MOS percent( "W" 0.1 "L" 0.1 ))
compareParameter( CAP percent( "value" 2 ))
compareParameter( RES percent( "value" 2 ))
compareParameter( DIO percent( "value" 0.1 ))
compareParameter( "hvpwhvnwdiop" percent( "value" 500 ))
mergeParallel(BJT noMerge)
**************************
If you will find:
compareParameter( MOS percent( "W" 0 "L" 0 ))
or something that looks like, then is better to know that you can put there a minimum tolerance like in my example. (0.1)
If you use Virtuoso XL and generate a layout driven by schematic, is easy to don't fit the schematics values for MOS, R, C when you change the number of transistor fingers and the acspect ratio of R or C, with 0.000000n % from the values. But because your tolerance is ZERO, you will have errors.
If your design can work well with a 0.1 tolerance, than you are covered and can change this in your LVS runset (rule) file.

Enjoy!
Gabriel.

related:

gabi71ro said:

Hello,


In the Runset (rule) file there is a part where are described tolerancies for al devices. You must check there and to change with a proper value.

Example:
**************************
compareParameter( MOS percent( "W" 0.1 "L" 0.1 ))
compareParameter( CAP percent( "value" 2 ))
compareParameter( RES percent( "value" 2 ))
compareParameter( DIO percent( "value" 0.1 ))
compareParameter( "hvpwhvnwdiop" percent( "value" 500 ))
mergeParallel(BJT noMerge)
**************************
If you will find:
compareParameter( MOS percent( "W" 0 "L" 0 ))
or something that looks like, then is better to know that you can put there a minimum tolerance like in my example. (0.1)
If you use Virtuoso XL and generate a layout driven by schematic, is easy to don't fit the schematics values for MOS, R, C when you change the number of transistor fingers and the acspect ratio of R or C, with 0.000000n % from the values. But because your tolerance is ZERO, you will have errors.
If your design can work well with a 0.1 tolerance, than you are covered and can change this in your LVS runset (rule) file.

Enjoy!
Gabriel.

Click to expand...

Thank you very much! I have solve this problem already,but still have some puzzles:
(!)in compare.rul,there is one line looks like" ignoreParameterNormalization( t )".Assura always gives error about this ,says cannot recognize avparameter.so i deleted this line and LVS pass.it is ok for reliability of this result?
(!!)using" compareParameter( MOS percent( "W" 0 "L" 0 ) )"can work in Solaris,why should be changed in Redhat?waht's the difference between these two operating system?

gabi71ro

hi.

The difference is that on RH you use Cadence 5...that is other release....They improve some things but other doesn't work.
I suppose that you can find some info in the Assura Diva Reference manual about I) and II).
If you can not, than I will look for you....but my vacation start, so I will not be available on the next two weeks.

Enjoy!

Gabriel.

assura tolerance setting lvs

Sometime the pdk gives the wrong CDL definition, that will cause the LVS parameter mismatch error