Lillese
Newbie level 1
Hi all,
I'm trying to get the worst delay path in my design between 2 scan cells (then I would like to test it on an ATE)
I used the command:
report_timing -true -from [all_registers -output_pins] -to [all_registers -data_pins]
but the path it found is false ! (I checked it using report -justify)
Did I forgot something or there isn't any true path in the design?
ps: I also tried by setting the variable true_delay_prove_false_backtrack_timing to -1 (unlimited)
Thanks
I'm trying to get the worst delay path in my design between 2 scan cells (then I would like to test it on an ATE)
I used the command:
report_timing -true -from [all_registers -output_pins] -to [all_registers -data_pins]
but the path it found is false ! (I checked it using report -justify)
Did I forgot something or there isn't any true path in the design?
ps: I also tried by setting the variable true_delay_prove_false_backtrack_timing to -1 (unlimited)
Thanks
