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For setup violations.. check the critical path and try to break that path by inserting a register between that combination logic.. or add buffer to increase delay of clock path to second registers..
For hold violations.... check the critical path where u get minimal propagation delay..
add buffer or delay cell to aviod hold violations..
when you get the timing violations, you may make sure:
1. the violations are real or not, firstly you should check your design constraint, such as clock definition, timing exception, environment setting etc...
2. if the violation are real, you should make sure that in the synthesis stage, you should solve all the setup violations by synthesis tools or communicate with the circuit designer. for the hold violation you can check them after CTS synthesis.
3. when in timing sign off stage, you also should analysis the Xtalk and OCV, of course the check corners you setted should adapt to your company i.e check all the corners when timing sign off.
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