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Verilog newbie problem

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davidgrm

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Hi

I am using QuartusII and it is not happy with the Verilog code below. It gives this error: Error: Can't resolve multiple constant drivers for net "BUSY"
I would appreciate it if someone could suggest how to do this. I want to set Busy on the Negedge of Strobe and I want to clear it on the negedge of PC_DATA_SENT. Strobe is an input and PC_DATA_SENT is coming from a different module. Thanks

BUSY is an output.

code snippet:

always @(negedge PC_Data_Sent)
begin
BUSY = 0;
end
always @(negedge STROBE)
begin
BUSY = 1;
end
 

You are assigning BUSY from two different always blocks.
This is not synthesizeable. Try this:

always @(negedge PC_Data_Sent or negedge STROBE)
begin
if (!STROBE)
BUSY <= 1'b1;
else if (!PC_Data_Sent)
BUSY <= 1'b0;
end
 

Thanks I will give it a try
 

Hey david,
Don't blame you .. this was probably my first mistake in verilog when i started coding too .... anyways the point is

* Busy is a wire / port
* You are trying to force a value on this from 2 different sources
-> This is the problem . You should drive any port / wire only from one source . If you try to drive 1 from one source and logic 0 from another what do you think is the output. simulation wise you'll simply say don't care .. but think hardware.

When coding in any hdl think hardware only then code.
 

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