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2-D array (verilog) synthesizable ?

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stevepre

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ncsim dumping arrays

I've been using VHDL for too long and don't know if 2-D array (verilog) is synthesizable or not...
 

yes, it's synthesizable
 

Thanks. And I just confirm that.
However, is there an easy way to dump the 2-D array in simulation (NCSIM)?
In Modelsim, it's right there. For VCS, I also know the way. But for NCSIM?
 

hi,
as to ncsim, I think no way
 

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