eng_islam
Member level 3
VCO Design and Test
i m working on CMOS VCO using .18 µ and i want to check the method of the design and testing on cadence "is there any initial condition have to be used "
i m working on CMOS VCO using .18 µ and i want to check the method of the design and testing on cadence "is there any initial condition have to be used "