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INL & DNL simulation using Spectre Cadence

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pnanda65675

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spice simulation dac dnl inl

i have this 10-bit pipeline ADC that operates at 6.75Mhz, i wanna test INL & DNL factor for my ADC, i knew it supposed to be done using transient analyses...what type of input i should give, i've differential input in to ADC. ANd how long u need run & how many hours does it takes???
 

inl and dnl simulation level

You can apply a slow input ramp (if differential as in your case you apply Vin+ from High level to low level while Vin- the opposite) and run a transient analysis. Also the ADC digital outputs must drive an ideal 10 bit DAC. The time for the ramp must have such a value that all the codes in the output of the DAC appear. I think that for an 10bit ADC it must be equal to 1024*Tclk.
In this way you will get in the output of the DAC, the input ramp quantized in steps. It is easy then, by comparing the input ramp to the output steps to calculate the INL and DNL (the procedure is written in many textbooks ).

Hope to helped you
 

spectre cadence

moisiad, have you still here?
And others,who can tell me how to compar the input ramp to the output steps to calculate the INL and DNL ?the procedure is written in what textbooks ? Because I have done the simulation as what you said above, but I don't know how to do next?
who can tell me for details to calculate?
 

    R

    Reenag

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spectre ramp

Hi
If you are using Cadence then they have Ideal 8 it ADC and DAC and INL and DNL measuring circuit written in verilogA. Just change the parameters to your requirement and use the measuring circuit at the output of your ADC.
BR
Vabzter
 

dnl in excel

Vabzter,what you say i know.
what I want to know is how to measure the DAC out, get DNL and INL?
 

inl and dnl simulations in cadence

Let me give you a Hspice compatible simulation method for your reference. You may ignore if not useful and see if there are insights from Cadence Spectre.

Transient input from PWL or input a a slow sine wave with say 1kHz.
The digital output is input to an ideal DAC modelled by Hspice and latched the analog data into a file using .measure statement at each conversion end.

Import the file into EXCEL and do calculation to measure DNL/INL. Check with analog device website and there are application notes showing how to use the results to calculate DNL/INL.
 

Re: inl and dnl simulation level

moisiad said:
You can apply a slow input ramp (if differential as in your case you apply Vin+ from High level to low level while Vin- the opposite) and run a transient analysis. Also the ADC digital outputs must drive an ideal 10 bit DAC. The time for the ramp must have such a value that all the codes in the output of the DAC appear. I think that for an 10bit ADC it must be equal to 1024*Tclk.
In this way you will get in the output of the DAC, the input ramp quantized in steps. It is easy then, by comparing the input ramp to the output steps to calculate the INL and DNL (the procedure is written in many textbooks ).

Hope to helped you
Click to expand...

how to apply slow input ramp in cadence
 

You got to do histogram testing. For simulation, i guess you may collect 20 samples per code. For 10-bit, u will need 1024x20 samples. The simulation time is going to take days....

of cos 20 samples is a very loose estimation.
 

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