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how to assign global reset signal to a input pin on stratix?

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liu_uestc

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i have finished a design in verilog;nmlr is the global reset signal and is low active; i have a development board of stratix(ep1s10f780c6). ac9 is stratix's

resetsignal input pin;i assign nmlr to ac9;but i find it can't be reseted; how can i do?
i shoud insert some special logic between the ac9 and nmlr ???it's a problem about
debounce circiut ?
 

Re: how to assign global reset signal to a input pin on stra

Hi

for every CPLD/FPGA, there a special and dedicated pin for reset. You must input your reset to that pin only. you can find this pin from the datasheet of CPLD/FPGA.


Regards,
Vishwa
 

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