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  1. #1
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    Error in the ADC causing Vin-Vout characteristic to shift

    Hi all

    In the sample and hold stage of a 1.5 bit pipeline ADC converter, when i get the Vin-Vout characteristic of the stage (the one with the triangles), i have noticed that the whole characteristic is shifted up by 60mV.
    I suppose that this is the systematic offset error which is not so critical (according to some books ). Am i wright? What are possible sources of this error?

    ("Sunking" i am waiting your help :D )

    Thanks

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    Re: Error in the ADC

    If you are using switched capacitor comparator in your sample and hold circuit, the offset voltage of your comparator may contribute to offset error of your adc. At high frequency the offset voltage of the comparator may be in milivolts range.



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    Re: Error in the ADC

    Just the S/H stage? as i know comparator is not adopted in this stage.
    The "offset" is between input such as sin-wave and sample output? This may be systematic offset, also maybe comes from non-ideal cmfb of amp. Try to adjust the cmfb and see what happen.

    Bg,


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    Error in the ADC

    yes, i gree with philipwang's.
    it maybe come from cmfb.


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  5. #5
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    Re: Error in the ADC

    Thanks all

    I have fixed the offset first of all by modifying the size of the output transistors in the OPAMP and second by using in the Sample and hold stage more linear capacitors instead of the MosCap. However from simulations i have noticed that this kind of error was not critical for the ADC operation.

    Now i am facing another problem (i hope the final). When i put an input ramp the output is the one illustrated in the first plot attached. As you see there are some big steps (missing codes) in specific points.

    In the second plot there is the residue from the first 4 stages. You can see that, starting from the second stage, the maximum level of all the triangles of the same stage is not the same. This is where i get the missing codes.

    Do you have something to propose?

    (The ADC is a 8-pipelined ADC with VDD=1V and f=40Mhz. Each stage has two reference levels 0.25V and 0.75V, i am not using in this case the 1.5bit stage configuration)

    Thank you very much



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