Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What's the best mirror ratio for the current from the tail current source of CMOS VCO

Status
Not open for further replies.
P

pi331133

Member level 2
Joined
Aug 9, 2004
Messages
46
Helped
4
Reputation
8
Reaction score
1
Trophy points
1,288
Activity points
520
For CMOS VCO design, T.H Lee and Ali said to bias VCO to the point before Voltage limited to achieve the best phase noise. And also the symmetry of the wavefrom can reduce the flicker noise upconversion. But there is a problem is, for the VCO with tail current source, if bias the circuit to achieve the symmetry, normally the tail current source will go into triode region. So anyone can help me on this, is it necessary to keep the current source in sat region? what is the best mirror ratio for the current from the tail current source of VCO and the transistor which diode connected for bias the tail current source?
 

cmos vco design

make the tail transistor is very large to make the volatge drop on it very small so it still be in sat and u can make ur headroom good

so u can get symmetric level

khouly
 

vco design bias

Hi,

Tail current device can cause low frequency noise which is AM noise and can be transfered to PM noise by varactor. The high frequency noise located at the harmonics of oscillating frequency also can degrade phase noise.

For the bias device, try to reduce the VDS of the currrent and need to keep them in sat. At lease keep them in sat when the oscillation waveform cross zero. Try to use large device to reduce VDS. The radio of the current mirror, normally, keep it less than 10. Thanks.
 

    P

    pi331133

    Points: 2
    Helpful Answer Positive Rating
design cmos vco

Dear friends

I am designibg vco for my PLL. can u pls guide me
1.what kind of PLL I can gofor?.
2.What are the sources / tutorial for VCO design.
3.What altenative archtectures are possible.
4. How we are controlling the frequncy of the VCO with voltage ( What is the relation between the control voltage and frewuency) This is very imp.Answer atleast this.

This I am designing as a part of my Mtech project.
yours
SavithRu
 

Re: CMOS VCO Design

khouly said:
make the tail transistor is very large to make the volatge drop on it very small so it still be in sat and u can make ur headroom good

so u can get symmetric level

khouly
Click to expand...

no, i dont agree, it will still fall into triode region if the volate drop is small or may be in sub-threhold region
 

CMOS VCO Design

increase the W/L ratio of the tail transistors, it worked in my VCO design
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top