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14th September 2005, 03:57 #1
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error [ibc] invalid bounds count + vcs error
use VCS compiler
I need a two dimension array
but VCS can not accept this syntax
EX :
......
....
for(i=0;i<RANGE; i=i+1)
data={chip.mem[i][127:63],chips.mem[i][127:63]}
.....
it seems VCS cannot accept a variable i ,
so
Q: How to solve this problem?

14th September 2005, 04:17 #2
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v2ks, verilog
Can you show us a little more code? Maybe a small complete module.

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14th September 2005, 05:06 #3
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vcs invalid bounds count
it's a simulation model,
two dimension array can let simulate more convinence
it's inside a task :
//===========
reg [32:0]mem[127:0];
reg [127:0]databuf;
task a;
input
output
int i;
begin i=0
@(.....)
repeat(33) begin
databuf={chip.mem[i][127:63],chips.mem[i][127:63]} ;
$display("...%h..............".databuf);
.........
end
i=i+1;
...
end
endtask
//===========use VCS

14th September 2005, 05:40 #4
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Re: [Help]Verilog Problem?
Can you post the ERROR that VCS generates for this part of code???

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14th September 2005, 11:31 #5
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[Help]Verilog Problem?
here is the error message
without +v2k argument
//=================
Error[V2KS] Verilog 2000 IEEE 13642000 syntax used. Please compile with +v2k
to support this construct
multidimensional select.
"./model/aa.inc", 11
//=================
with +v2k argument
Error[IBC] Invalid bounds count
The following access has an invalid number of indices.
"./model/aa.inc", 11:
pattern.chip.mem[i][127][63]
1error
By the way
my VCS is version 6.1 running on Solaris!

14th September 2005, 11:32 #6
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[Help]Verilog Problem?
Basically, you can not separate the vector like
m[i][100:90], you should use
wire [11:0]x=m[i][100:90];
then use m[i][x1:0]

14th September 2005, 11:36 #7
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Re: [Help]Verilog Problem?
Originally Posted by debussy1765
Would you pls give me a complete example
I dont understand the statement
wire [11:0]x=m[i][100:90];
would you pls explain more detail ?

15th September 2005, 02:25 #8
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[Help]Verilog Problem?
guy, it's easy.
do like this.
reg [127:0] temp;
temp = chip.mem[i];
data={temp[127:63],temp[127:63]} ;
have a try.

16th September 2005, 11:39 #9
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Re: [Help]Verilog Problem?
Originally Posted by billjoy
Hi, you define the type databuf as a 128bit variable(register); however you assign a vector to this scalable varialbe. I think you maybe made a mistake in your coding.
The accessing width of the memory is 128bit or as you defined 32bit?
For the assignment mechansim, please refer to the extension of verilog2001

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16th September 2005, 12:32 #10
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Re: [Help]Verilog Problem?
If you had a later VCS version, using SystemVerilog mode when you compile, would allow your code.
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