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Voltage booster for Memories Circuit

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tok47

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Dear ALL,

This is the first time I due with this circuit. So, I wish wish to have some basic rule of thumb of design a voltage booster.

Some info regarding my circuit. There were a 3 stage boosting for 1.8v application. The desired output is around 5v. In each of the stage, I parrallel 3 capacitors with different values. And there some logic to let the voltage pass from 1 stage to another.

Question :
1. Is it better to parallel 3 same capacitance capacitor or just use a single capacitance ?

2. How can I simulated the circuit performance against VCC (sweep VCC)?

3. How to reduce the effect of change of VCC to the output?

thanks


rdgs
tok
 

tok47 said:
Dear ALL,

This is the first time I due with this circuit. So, I wish wish to have some basic rule of thumb of design a voltage booster.

Some info regarding my circuit. There were a 3 stage boosting for 1.8v application. The desired output is around 5v. In each of the stage, I parrallel 3 capacitors with different values. And there some logic to let the voltage pass from 1 stage to another.

Question :
1. Is it better to parallel 3 same capacitance capacitor or just use a single capacitance ?

2. How can I simulated the circuit performance against VCC (sweep VCC)?

3. How to reduce the effect of change of VCC to the output?

thanks


rdgs
tok
Click to expand...

1)
it relates to the ESR and ESL of the capacitor. ESR affects the ripple voltage, ESL affects the resonance frequency of your capacitor. So, pls choose whether using single cap. or 3 caps in parallel accordingly.

2)
I assume you are doing charge bump. Thus you need to simulate the line regulation using transient mode case by case.

3)
Most likely, adding a LDR after the output of the chare bump......

Scotte
 

Can you please brief me more about ESR and ESL?

Do I need to consider these 2 terms in IC design?

Thanks
 

tok47 said:
Can you please brief me more about ESR and ESL?

Do I need to consider these 2 terms in IC design?

Thanks
Click to expand...

ESR = Equivalent Series Resistance
ESL = Equivalent Series Inductance

so a capacitor, no matter it is discrete or on-chip (e.g. IC technology) can be modelled as a capacitor (C), a ESR (R) and a ESL (L) in series.

From this model, you can understand the ESL and the C limits your operating frequency as it sets a resonance.

Moreover, ESR introduce a ripple voltage when there is pulsating current in or out the capacitor.

Hope this help
Scottie
 

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    tok47

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