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How to solve both setup and hold violation without changing the clock paths

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dynamicdude

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Can anybody tell me how to react to both setup and hold violation in the circuit perspective without changing the clock paths?

If there are any relevant documents please let me know.
 

Re: Timing violation?

for hold time violations, we can add buffer before DFF's D input to increase

data delay; for setup time violation, the measure that we can take is

re-synthesis with more stringent constraints or re-code RTL code!


dynamicdude said:
Can anybody tell me how to react to both setup and hold violation in the circuit perspective without changing the clock paths?

If there are any relevant documents please let me know.
Click to expand...
 

Re: Timing violation?

hi
go thro your code to find any unuwanted combo logic infered and remove it.
pipelining your design can help
 
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