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23rd March 2020, 16:54 #1
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Adding '1' to a std_logic_vector in VHDL
I'm having an error about adding 1 to a std_logic_vector in VHDl.
Here's the code: It's a 74LS163 Synchronous Binary Counter code.
Code:LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; entity AAC2M2P1 is port ( CP: in std_logic;  clock SR: in std_logic;  Active low, synchronous reset P: in std_logic_vector(3 downto 0);  Parallel input PE: in std_logic;  Parallel Enable (Load) CEP: in std_logic;  Count enable parallel input CET: in std_logic;  Count enable trickle input Q: out std_logic_vector(3 downto 0); TC: out std_logic  Terminal Count ); end AAC2M2P1; architecture LS163 of AAC2M2P1 is signal temp: std_logic_vector(0 to 3); signal RCO: std_logic; begin process(CP, SR, PE) begin if (SR = '1') then temp <= "0000"; elsif (rising_edge(CP)) then if (PE = '0') then temp <= P; if (temp = "1111") then temp <= "0000"; RCO <= '1'; else temp <= temp + 1; ERROR RCO <= '0'; end if; end if; end if; end process; Q <= temp; TC <= RCO; end LS163;
I tried using x"1", x"0001" and '1' but all of these didn't worked.
Also, how should I write the code for using CEP and CET as count enables.Last edited by chandlerbing65nm; 23rd March 2020 at 16:59.

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23rd March 2020, 19:56 #2
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Re: Adding '1' to a std_logic_vector in VHDL
Make temp unsigned, then you can perform arithmetic on it.
When you output it to Q, cast it as std_logic_vector
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23rd March 2020, 20:15 #3
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Re: Adding '1' to a std_logic_vector in VHDL
adding std_logic_vectors is not supported in the numeric_std library as fourtytwo suggests use unsigned which does support arithmetic operations.
Also, how should I write the code for using CEP and CET as count enables.Code VHDL  [expand] 1 2 3 4 5 6 7 8
process(clk) begin if rising_edge(clk) then if (CEP = '1') then  counts when high CEP_enabled_counter <= CEP_enabled_counter + 1; end if; end if; end process;
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23rd March 2020, 22:01 #4
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Re: Adding '1' to a std_logic_vector in VHDL
Or use VHDL 2008. The numeric_std_unsigned package allows unsigned arithmatic on std_logic_vector, even allowing the perenial student compilation error  adding a std_logic to a std_logic_vector
Code VHDL  [expand] 1 2 3 4 5 6 7 8 9 10
use ieee.numeric_std_unsigned.all; signal cnt : std_logic_vector(15 downto 0); process(clk) begin if rising_edge(clk) cnt <= cnt + '1'; end if; end process;

23rd March 2020, 22:31 #5
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Re: Adding '1' to a std_logic_vector in VHDL
I got this final code:
Code:architecture LS163 of AAC2M2P1 is signal temp: unsigned(3 downto 0); signal RCO: std_logic; signal count_enables: std_logic; begin count_enables <= CEP and CET; process(CP, SR, PE, P) begin if (SR = '0') then temp <= "0000"; elsif (rising_edge(CP)) then if (PE = '1') then temp <= unsigned(P); if count_enables = '1' then if (temp = "1111") then RCO <= '1'; temp <= "0000"; else RCO <= '0'; temp <= temp + 1; end if; end if; end if; end if; end process; Q <= std_logic_vector(temp); TC <= RCO; end LS163;
But the auto grader scored it 5/10 (at online course), (It count up until F for a given time period though). It must be that some of the functions of 74LS163 is not used or misused. If someone could look ever what I'm missing, that will be helpful. Thanks

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24th March 2020, 10:05 #6
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Re: Adding '1' to a std_logic_vector in VHDL
The TC output is wrong, should be '1' when the counter is "1111" and CET = '1'.
The parallel load is wrong, should happen when PE = '0', regardless of CEP and CET.
An unsigned signal will wrap automatically from "1111" to "0000", so you don't need code for that.
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24th March 2020, 13:51 #7
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Re: Adding '1' to a std_logic_vector in VHDL
I got the right answer with 1 error in TC. Scored 9/10 but still curious what is the error in TC.
Here's the updated code.
Code:architecture LS163 of AAC2M2P1 is signal temp: unsigned(3 downto 0); signal RCO: std_logic; signal count_enables: std_logic; begin count_enables <= CEP and CET; counter: process(CP) begin if rising_edge(CP) then if SR = '0' then temp <= "0000"; elsif SR = '1' and PE = '0' then temp <= unsigned(P); elsif SR = '1' and PE = '1' and count_enables = '1' then temp <= temp + 1; end if; end if; end process counter; Q <= std_logic_vector(temp); carry: process(P, CET) begin if CET = '1' then RCO <= P(0) and P(1) and P(2) and P(3); else RCO <= '0'; end if; end process carry; TC <= RCO; end LS163;

24th March 2020, 14:18 #8
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Re: Adding '1' to a std_logic_vector in VHDL
RCO is evaluating P input but should evaluate temp respectively Q.
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