reservevoltage
Newbie level 4
Hi there,
Currently ı have worked on cpld demo board which name is cpld c-m240 (clone board). The board has epm240t100c5n cpld.
In this board, ı have tried to communicate with PC by implementing UART.
However, my code is not working properly on the board.
I'm waiting your a brilliant advice.
test code
tx code
Currently ı have worked on cpld demo board which name is cpld c-m240 (clone board). The board has epm240t100c5n cpld.
In this board, ı have tried to communicate with PC by implementing UART.
However, my code is not working properly on the board.
I'm waiting your a brilliant advice.
test code
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test is
port(
start : in std_logic;
clk: in std_logic;
rslt: out std_logic);
end test;
architecture davranis of test is
COMPONENT uart_tx
PORT(
clk: in std_logic;
reset: in std_logic;
inpt : in std_logic_vector(7 downto 0);
send: in std_logic;
ok: out std_logic;
rslt: out std_logic);
END COMPONENT;
type d_type is array (0 to 15) of std_logic_vector(7 downto 0);
constant data1: d_type:=(x"22",x"53",x"45",x"4c",x"41",x"4D",x"20",x"46",x"50",x"47",x"41",x"22",x"00",x"00",x"00",x"00");
signal counter : std_logic_vector(3 downto 0):=(others=>'0');
signal counter_next : std_logic_vector(3 downto 0):=(others=>'0');
signal active : std_logic;
signal ok : std_logic;
signal inpt : std_logic_vector(7 downto 0);
begin
Inst_uart_tx : uart_tx PORT MAP (clk=>clk,reset=>'0',inpt=>inpt,send=>active, ok=>ok,rslt=>rslt);
process(clk)
begin
if rising_edge(clk) then
counter<=counter_next;
end if;
end process;
active<='1' when start='1' and counter <"1101" else '0';
counter_next<=counter+1 when ok='1' else counter;
inpt<=data1(conv_integer(counter));
end davranis;
tx code
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity uart_tx is
port
(
clk,reset,send : in std_logic;
inpt : in std_logic_vector(7 downto 0);
ok,rslt : out std_logic
);
end uart_tx;
architecture davranis of uart_tx is
constant clk_index:integer:=5200;
type statu_index is(wait_txd,start_txd,send_txd,stop_txd);
signal statu,statu_next: statu_index;
signal N,N_next:integer;
signal counter,counter_next: integer;
signal data,data_next: std_logic:='0';
begin
Bellek:process(clk,reset)
begin
if reset='1' then
statu<=wait_txd;
counter<=0;
data<='1';
N<=0;
elsif clk='1' and clk'event then
statu<=statu_next;
counter<=counter_next;
data<=data_next;
N<=N_next;
end if;
end process;
kombinasyonal: process(statu,counter,N,send,inpt,data)
begin
statu_next<=statu;
counter_next<=counter;
data_next<='1';
N_next<=N;
ok<='0';
case statu is
when wait_txd=>
if send='1' then
statu_next<=start_txd;
end if;
when start_txd=>
counter_next<=counter+1;
data_next<='0';
if counter=clk_index then
counter_next<=0;
statu_next<=send_txd;
end if;
when send_txd=>
counter_next<=counter+1;
data_next<=inpt(N);
if counter=clk_index then
if N=7 then
statu_next<=stop_txd;
N_next<=0;
else
N_next<=N+1;
end if;
counter_next<=0;
end if;
when stop_txd=>
counter_next<=counter+1;
if counter= clk_index then
counter_next<=0;
ok<='1';
statu_next<=wait_txd;
end if;
end case;
end process;
rslt<=data;
end davranis;