chandlerbing65nm
Member level 5
Hi folks,
I have a problem with my random led blinker on fpga.
3-4 leds are turning "on" at the same time.
Although it is random, what I want is that only one led will be "on" at a time.
It seems that there is a problem with my code that the leds are overlapping there on and off states.
Before one led turns off, another led will turn on. This makes them overlap.
-- moderator added code inline --
I have a problem with my random led blinker on fpga.
3-4 leds are turning "on" at the same time.
Although it is random, what I want is that only one led will be "on" at a time.
It seems that there is a problem with my code that the leds are overlapping there on and off states.
Before one led turns off, another led will turn on. This makes them overlap.
-- moderator added code inline --
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // PROGRAM "Quartus Prime" // VERSION "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" // CREATED "Sat Feb 22 12:52:13 2020" module WhackAMole( clk, reset, LED ); input wire clk; input wire reset; output wire [7:0] LED; wire [9:0] SYNTHESIZED_WIRE_0; blinking_leds b2v_inst( .clk(clk), .reset(reset), .rnd(SYNTHESIZED_WIRE_0), .LED(LED)); randomnumbergenerator b2v_inst1( .clk(clk), .reset(reset), .rnd(SYNTHESIZED_WIRE_0)); endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 module randomnumbergenerator ( input clk, input reset, output reg [9:0] rnd ); wire feedback; wire [9:0] lfsr_next; //An LFSR cannot have an all 0 state, thus reset to non-zero value reg [9:0] reset_value = 13; reg [9:0] lfsr; reg [31:0] count; reg [31:0] counter; // pragma translate_off integer f; initial begin f = $fopen("output.txt","w"); end // pragma translate_on always @ (posedge clk or posedge reset) begin if (reset) begin lfsr <= reset_value; count <= 32'hF; rnd <= 0; end else begin lfsr <= lfsr_next; count <= count + 1; // a new random value is ready if (count == 32'd9) begin count <= 0; rnd <= lfsr%8; //assign the lfsr number to output after 10 shifts // pragma translate_off $fwrite(f,"%0d\n",rnd); // pragma translate_on end end end // X10+x7 assign feedback = lfsr[9] ^ lfsr[6]; assign lfsr_next = {lfsr[8:0], feedback}; // pragma translate_off always @ (*) begin if (rnd == reset_value) begin $fclose(f); $finish(); end end // pragma translate_on endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 module blinking_leds ( input clk, input reset, input [9:0] rnd, output [7:0] LED); reg [31:0] counter; reg [7:0] LED_status; initial begin counter <= 32'b0; LED_status <= 0; end always @(posedge clk or posedge reset) begin if (reset) begin counter <= 32'b0; LED_status <= 0; end else if (counter > 5000000) begin case(rnd) 10'b0000000000: LED_status[0] <= !LED_status[0]; //0 10'b0000000001: LED_status[1] <= !LED_status[1]; //1 10'b0000000010: LED_status[2] <= !LED_status[2]; //2 10'b0000000011: LED_status[3] <= !LED_status[3]; //3 10'b0000000100: LED_status[4] <= !LED_status[4]; //4 10'b0000000101: LED_status[5] <= !LED_status[5]; //5 10'b0000000110: LED_status[6] <= !LED_status[6]; //6 10'b0000000111: LED_status[7] <= !LED_status[7]; //7 endcase counter <= 32'b0; end else begin counter <= counter + 1'b1; end end assign LED = LED_status; endmodule
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