yefj
Advanced Member level 4
Hello , In the the photo bellow we have a common mode feedback circuit.
Mismatch in currents causes a mismatch in voltages which is amplified and connected to the gates of BIAS pmos transistors on top.
But how exactly it fixes the problem ?
The output of the OPAMP is an AC signal ,its not a constant DC point, how does exactly putting an AMPLIFIED AC signal to the pmos gate solves this problem.We could design this mismatch amplifier to be 30dB gain or 20 dB gain ,both of them will create a different amplitude signal of the gates pmos.
In my intuition i see the transistor as ressistors , so when we have a high voltage on one side then we need to increase the PMOS rds ressitance in order to get a lower output signal. but here we get the same signal to both gates of PMOSES on both sides.so we make the same increase/decrease of output voltate on both sides.
How the mismatch fixing goes exactly?
Thanks.
Mismatch in currents causes a mismatch in voltages which is amplified and connected to the gates of BIAS pmos transistors on top.
But how exactly it fixes the problem ?
The output of the OPAMP is an AC signal ,its not a constant DC point, how does exactly putting an AMPLIFIED AC signal to the pmos gate solves this problem.We could design this mismatch amplifier to be 30dB gain or 20 dB gain ,both of them will create a different amplitude signal of the gates pmos.
In my intuition i see the transistor as ressistors , so when we have a high voltage on one side then we need to increase the PMOS rds ressitance in order to get a lower output signal. but here we get the same signal to both gates of PMOSES on both sides.so we make the same increase/decrease of output voltate on both sides.
How the mismatch fixing goes exactly?
Thanks.
Last edited: