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    how to generate 4MHz clock from 2 MHz clock.

    Hi,

    I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz.

    I had read about using rising and falling edge detectors but they fail to give 50% duty cycle.

    can DDS(direct digital synthesizer ) convert 2MHz clock frequency into 4MHz frequency??

    what are the other methods to do that??

    Regards
    Ankit

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    Re: how to generate 4MHz clock from 2 MHz clock.

    This cheap IC does perfect job for your purpose:
    https://www.maximintegrated.com/en/d...es/3/3327.html



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    Re: how to generate 4MHz clock from 2 MHz clock.

    If you have a higher frequency clock available, a digital PLL can generate the 4 MHz clock, however limited to the time resolution of the system clock. Ultimately, you can phase lock an auxiliary high frequency clock to the 2 MHz input, using MMCM dynamic phase shift feature and some user logic.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    Hi,

    Which FPGA are you talking about?

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    Quote Originally Posted by KlausST View Post
    Hi,

    Which FPGA are you talking about?

    Klaus
    Must be a Xilinx part (MMCM/PLL), but can't tell which one as more than one of the families has that primitive. Though it can be narrowed down with the OP's statement that the wizard says the FPGA can only support a lower frequency of 10 MHz for the PLL input clock.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    10 MHz minimal clock input frequency is common series 7 MMCM spec as far as I'm aware of.



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    Re: how to generate 4MHz clock from 2 MHz clock.

    The OP has posted the same Q in Xilinx forums yesterday and did not provide sufficient details in order to answer his Q.
    My answer to him would be the same here as there.

    The PLL/MMCM inside the Arty board is capable of min 10Mz o/p or more. ads-ee/FvM have also pointed that out.
    This was the reason why it was asked to him the source of this 2MHz clk and to it there has been no info from the OP.

    Dear OP, no matter in forum you go, if you are not providing sufficient details, you won't get proper answers.
    Last edited by dpaul; 14th February 2020 at 09:32.
    FPGA enthusiast!


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    Re: how to generate 4MHz clock from 2 MHz clock.

    Possible solutions have been sketched, but the application requirements are yet unknown.



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