miso156
Junior Member level 2
Hello All,
I need to design a clock devider using PBJT. So it should look like this:
However, when i do it from PBJT, the output starts oscilate due to immediate changes of D input, when clock is high.
Id like to build this to hold the output until next positive level of CLK come. Maybe it will be necessary to use another SR flop, or some logic, i dont care, but do not to use edge triggering.
I need to design a clock devider using PBJT. So it should look like this:
However, when i do it from PBJT, the output starts oscilate due to immediate changes of D input, when clock is high.
Id like to build this to hold the output until next positive level of CLK come. Maybe it will be necessary to use another SR flop, or some logic, i dont care, but do not to use edge triggering.