mohit11511
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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 library ieee; -- line 1 use ieee.std_logic_1164.all; -- line 2 -- line 3 entity find_errors is port( -- line 4 a: in std_logic_vector(0 to 3); -- line 5 b: out std_logic_vector(3 to 0); -- line 6 c: in std_logic_vector(5 downto 0)); -- line 7 end find_errors; -- line 8 -- line 9 architecture not_good of find_errors is -- line 10 begin -- line 11 my_label: process -- line 12 begin -- line 13 if (c = ("00" & x"F")) then -- line 14 b <= a; -- line 15 else -- line 16 b <= "0101"; -- line 17 end if; -- line 18 end process; -- line 19 end not_good;
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