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  1. #1
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    Safe value of Vgs in sub-threshold design (4.5nUT < Vgs - Vth < -2nUT)?

    Hello,

    I am designing circuit (using 0.18um). Usually, by biasing Vgs < Vthreshold of MOSFET, we can push MOS into sub-threshold region. My curious question is: How much value of Vgs is "good" as a "rule of thumb"?

    I have referenced to "Trade-offs and optimization in Analog CMOS design" book, and they supplied a good reference (please check the figure below). It seems to be good from this book is that we should bias MOS
    such that -4.5nUT < Vgs - Vth < -2nUT, which is equivalent to approximate value in a range of: -163 mV < Vgs - Vth < -72 mV (n is the slope factor defined by EKV model from EPFL, UT = kT/q is the thermal voltage).

    Could you guys confirm or give out any recommendations?

    Thank you!


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  2. #2
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    Re: Safe value of Vgs in sub-threshold design (4.5nUT < Vgs - Vth < -2nUT)?

    I guess this can vary depending on technology node. But one not so difficult way to visually see when the transistor enters subthreshold is to plot gm/Id vs Vgs (or vs Vgs-Vth).



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