Sambhav_1
Full Member level 2
Hi,
I am designing a differential folded cascode with both P and N-mos input transistor stages due to my different input common modes.
During my transient analysis while running across the corners i am getting some offset of 70mv at worst between the two outputs.
How can i minimize this offset.
Note: I am giving a 0.3mV offset at the input and these results are in pre layout simulations.
Thanks
I am designing a differential folded cascode with both P and N-mos input transistor stages due to my different input common modes.
During my transient analysis while running across the corners i am getting some offset of 70mv at worst between the two outputs.
How can i minimize this offset.
Note: I am giving a 0.3mV offset at the input and these results are in pre layout simulations.
Thanks